參數(shù)資料
型號： GS4901BCNE3
廠商： Gennum Corporation
英文描述： SD Clock and Timing Generator with GENLOCK
中文描述： 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁數(shù)： 72/95頁
文件大?。?/td> 898K
代理商： GS4901BCNE3
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
72 of 95
Constcf_Genlock
24h
15-8
Crash_Time - controls the crash lock period of video
PLL locking process. This time contributes to the total
PLL Lock Time given in the AC Characteristics Table.
The time of the crash process in H reference periods is
determined by [Crash_Time x 4] + 1.
The default value of these bits will vary depending on
the output video standard selected.
Reference:
Section 3.6.1 on page 47
R/W
–
24h
7-3
Lock_Lost_Threshold - controls the threshold of the lock
indication circuit. A larger value programmed in this
register can increase the stability of the LOCK_LOST
output signal when the input H reference signal is
subject to large amounts of low frequency jitter. A larger
value in this register will also increase the lock indication
time, although not the actual lock time of the device.
The default value of these bits will vary depending on
the output video standard selected.
R/W
–
24h
2-0
Run_Window - controls the output frequency error in the
case of a missing or mis-timed H reference transition.
The default value of this register allows the device to
maintain genlock through one missing input H pulse.
This feature can be disabled by programming
Run_Window = 000b. In this case, the device will
immediately react to any disturbance of the input H
signal.
The default value of these bits will vary depending on
the output video standard selected.
Reference:
Section 3.5.3 on page 44
R/W
–
RSVD
25h
–
Reserved.
–
–
Video_Cap_Genlock
26h
15-6
Reserved. Set these bits to zero when writing to 26h.
–
–
26h
5-0
Control signal to adjust loop bandwidth of video genlock
block.
The value programmed in this register must be between
10 and Video_Res_Genlock - 21.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Section 3.6.2 on page 48
R/W
–
Video_Res_Genlock
27h
15-6
Reserved. Set these bits to zero when writing to 27h.
–
–
27h
5-0
Control signal to adjust loop bandwidth of video genlock
block.
The value programmed in this register must be between
32 and 42.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Section 3.6.2 on page 48
R/W
–
RSVD
28h-2Bh
–
Reserved
–
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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