參數(shù)資料
型號: GS4901BCNE3
廠商: Gennum Corporation
英文描述: SD Clock and Timing Generator with GENLOCK
中文描述: 統(tǒng)計時鐘和定時發(fā)生器鎖相
文件頁數(shù): 12/95頁
文件大?。?/td> 898K
代理商: GS4901BCNE3
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
12 of 95
19
FSYNC
Non
Synchronous
Input
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The FSYNC external reference signal is applied to this pin by the
application layer.
The first field is defined as the field in which the first broad pulse (also
known as serration) is in the first half of a line. The FSYNC signal should
be set HIGH during the first field for sync-based references.
Then this signal must adhere to one of the 36 defined video standards
supported by the device. In this mode of operation, the FSYNC input
provides an odd/even field input reference.
The FSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer.
Section 1.4
on page 20
describes the 36 video formats recognized by the
GS4901B/GS4900B.
For blanking-based references, the FSYNC signal should be set HIGH
during the second field.
NOTE: If the input reference format does not include an F sync signal,
this pin should be held LOW.
27, 25, 24,
23, 22, 21
VID_STD[5:0]
Non
Synchronous
Input
CONTROL SIGNAL INPUTS
Signal levels are LVCMOS/LVTTL compatible.
Video Standard Select.
Used to select the desired video format for video clock and timing signal
generation.
4 different video sample clocks, as well as 9 different video format timing
signal outputs may be selected using these pins.
NOTE: The VID_STD[5:4] pins should be grounded by the application
layer since these pins are not required to select output video standards 1
to 10.
For details on the supported video standards and video clock frequency
selection, please see
Section 1.4 on page 20
.
26, 44
CORE_VDD
Power
Supply
Most positive power supply connection for the digital core. Connect to
+1.8V DC.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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