參數(shù)資料
型號(hào)： GS4901BCNE3
廠商： Gennum Corporation
英文描述： SD Clock and Timing Generator with GENLOCK
中文描述： 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 70/95頁(yè)
文件大?。?/td> 898K
代理商： GS4901BCNE3
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
70 of 95
10FID_AFS_Reset
1Ah
15-4
Reserved. Set these bits to zero when writing to 1Ah.
–
–
1Ah
3
AFS_Reset (GS4901B only) - set this bit HIGH to use
Reset_Sync (bit 0 of register 1Ah) to reset the output
AFS pulse.
NOTE: This bit will remain LOW in the GS4900B. Set
this bit LOW when writing to address 1Ah of the
GS4900B.
Reference:
Section 3.7.2.1 on page 55
R/W
0
1Ah
2
10FID_Reset - set this bit HIGH to use Reset_Sync (bit
0 of register 1Ah) to reset the output 10FID pulse.
NOTE: If a 10FID input signal is not provided to the
device, the user must generate a reset using this bit to
initiate the 10FID timing output. In this case, the 10FID
input pin must be grounded.
Reference:
Section 3.7.2.1 on page 55
R/W
0
1Ah
1
Reserved. Set this bit to zero when writing to 1Ah.
–
–
1Ah
0
Reset_Sync - resets the pulses described in bits 2, and
3 above.
The reset pulse is generated if this bit is pulsed (LOW to
HIGH to LOW) during the output frame immediately
prior to the frame the reset is to occur. This reset will
operate independently of any other resets, for example
from the reference input.
R/W
0
H_Offset
1Bh
15-0
The output H signal may be delayed with respect to the
input reference by the number of pixels programmed in
this register. (See
Section 3.2.1.1 on page 35
).
The value programmed in this register should not
exceed the maximum number of clock periods per line
of the outgoing standard. Horizontal advances may be
achieved by programming a value equal to the
maximum allowable offset minus the desired advance.
NOTE: This register is internally read by the device
once per field. At that time any new value programmed
is sent to the internal offset circuitry.
Reference:
Section 3.2.1.1 on page 35
R/W
0
V_Offset
1Ch
15-0
The output V signal may be delayed with respect to the
input reference by the number of lines programmed in
this register. (See
Section 3.2.1.1 on page 35
).
The value programmed in this register should not
exceed the maximum number of lines per frame of the
outgoing standard. Vertical advances may be achieved
by programming a value equal to the maximum
allowable offset minus the desired advance.
NOTE: This register is internally read by the device
once per field. At that time any new value programmed
is sent to the internal offset circuitry.
Reference:
Section 3.2.1.1 on page 35
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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