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參數(shù)資料
| 型號： | GS4901BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 43/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4901BCNE3 |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
43 of 95
3.5.2 Input Reference Validity
Before the device attempts to operate in Genlock mode, the input signals applied
to HSYNC and VSYNC must be valid (SD references only) and must conform to
one of the recognized and enabled video standards, as described in
Section 1.4 on
page 20
.
For an SD input reference signal to be considered valid, the periodicity of HSYNC
must be between 29.66us and 70us, and the periodicity of VSYNC must be
between 16ms and 25ms. The FSYNC signal is not essential for validity. The
REF_LOST pin will be set LOW once the SD input reference signal is determined
to be valid.
For HD input reference signals where the user has set the HD_Reference_Enable
bit of register 82h[7] HIGH, the device will not measure signal validity. In this case,
the REF_LOST pin will be LOW whenever any reference signal is present on the
input.
The device then compares the timing parameters of the input reference signal to
each of the video standards that has been enabled in the the
Reference_Standard_Disable register (there may be up to 36 video standards if all
HD standards are enabled). The device will then determine if the input reference is
one of the enabled and recognized standards. If it is, the VID_STD[5:0] value for
the format is written to the Input_Standard register at address 0Fh of the host
interface. If the reference format is unrecognized or disabled, 00h is programmed
in this register.
Once a reference signal is recognized by the device, VSYNC and FSYNC will no
longer be monitored. Loss of signal on these pins will not affect the operation of the
device.
If the REF_LOST pin is HIGH, or if the input signal is unrecognized as one of the
enable video formats, the GENLOCK pin should not be set LOW.
The REF_LOST output pin may also be read via bit 0 of the Genlock_Status
register (see
Section 3.10.3 on page 66
).
3.5.2.1 Ambiguous Standard Selection
There are some standards with identical H, V, and F timing parameters, such that
the GS4901B/GS4900B’s reference format detector cannot distinguish between
them.
Table 3-2
groups standards with shared H, V, and F periods. Using the
Amb_Std_Sel register at address 10h of the host interface, the user may select
their choice of standard to be identified with a particular set of measurements. For
example, to have 1716 clocks of 27MHz per line with 525 lines per frame identified
as 4fsc 525, program Amb_Std_Sel[10:0] = XXX10XXXXXX, where ‘X’ signifies
‘don’t care’.
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相關代理商/技術參數(shù) |
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|---|---|
| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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