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| 型號(hào)： | GS4901BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相 |
| 文件頁數(shù)： | 36/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4901BCNE3 |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
36 of 95
V_Offset (1Ch) - the difference between the reference VSYNC signal and the
output V Sync and/or V Blanking in lines, with a control range of zero to +1
frame. All line-based timing output signals will be delayed by the vertical offset
programmed in this register.
The encoding scheme for the Clock_Phase_Offset register (1Dh) is shown in
Table 3-1
. The offset programmed will be in the positive direction. Note that the
step size will depend on the frequency of the output video clock.
The value programmed in the H_Offset register (1Bh) must not exceed the
maximum number of clock periods per line of the outgoing video standard.
Similarly, the value programmed in the V_Offset register (1Ch) must not exceed
the maximum number of lines per frame of the outgoing standard. Both horizontal
and vertical offsets will be in the positive direction. Negative offsets (advances) are
achieved by programming a value in the appropriate register equal to the maximum
allowable offset minus the desired advance.
NOTES:
1. The device will delay all output timing signals by 2 PCLKs relative to the input
HSYNC reference. This will occur even when the H_Offset register is not
programmed. The user may compensate for this delay by subtracting 2 PCLK
cycles from the desired horizontal offset before loading the value into the host
interface.
2. For both sync and blanking-based input references, the device will advance all
line-based output timing signals by 1 line relative to the input VSYNC
reference for all output standards except VID_STD[5:0] = 4, 6, and 8. This will
occur even when the V_Offset register is not programmed. The user may
compensate for this advance by adding 1 line to the desired vertical offset
before loading this value into the register.
Table 3-1: Clock_Phase_Offset[15:0] Encoding Scheme
VID_STD[5:0]
Setting
Output Video Clock
Frequency
Step Size
(Fraction
of a
PCLK)
Maximum
Number of
Steps
Bits Required to
Set the Number
of Steps
Clock_Phase_Offset
[15:0] Settings
1
f
PCLK
< 20MHz
511
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
8
000001b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
3-6
20MHz < f
PCLK
< 40MHz
255
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
7
000010b
7
b
6
b
5
b
4
0b
3
b
2
b
1
b
0
7-10
40MHz < f
PCLK
< 54MHz
127
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
6
000100b
6
b
5
b
4
00b
3
b
2
b
1
b
0
Note: Program Clock_Phase_Offset = 0000 0000 0000 0000b to achieve a zero clock phase offset.
512
---1
256
---1
128
---1
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