參數(shù)資料
型號： GS1559-CBE2
廠商： Gennum Corporation
英文描述： GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver
中文描述： GS1559的HD - LINX進程，商標第二多速率解串器與環(huán)通電纜驅(qū)動器
文件頁數(shù)： 8/74頁
文件大?。?/td> 686K
代理商： GS1559-CBE2
GS1559 Data Sheet
30572 - 4
July 2005
8 of 74
B7
FW_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is used in
the extraction and generation of TRS timing signals, in automatic video
standards detection, and in manual switch line lock handling.
When set LOW, the internal flywheel is disabled and TRS correction and
insertion is unavailable.
B8, F8, J8
IO_GND
–
Power
Ground connection for digital I/O buffers. Connect to digital GND.
C1
BUFF_VDD
–
Power
Power supply connection for the serial digital input buffers. Connect to
+1.8V DC analog.
C2
PD_VDD
–
Power
Power supply connection for the phase detector. Connect to +1.8V DC
analog.
C3
PDBUFF_GND
–
Power
Ground connection for the phase detector and serial digital input buffers.
Connect to analog GND.
C6
MASTER/SLAVE
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to determine the input / output selection for the DVB_ASI, SD/HD,
RC_BYP and SMPTE_BYPASS pins.
When set HIGH, the GS1559 is set to operate in master mode where
DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become status signal
output pins set by the device. In this mode, the GS1559 will automatically
detect, reclock, deserialize and process SD SMPTE, HD SMPTE, or
DVB-ASI input data.
When set LOW, the GS1559 is set to operate in slave mode where
DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become control signal
input pins. In this mode, the application layer must set these external
device pins for the correct reception of either SMPTE or DVB-ASI data.
Slave mode also supports the reclocking and deserializing of data not
conforming to SMPTE or DVB-ASI streams.
C7
RC_BYP
Non
Synchronous
Input
/Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The RC_BYP signal will be HIGH only when the device has successfully
locked to a SMPTE or DVB-ASI compliant input data stream. In this case,
the serial digital loop-through output will be a reclocked version of the
input.
The RC_BYP signal will be LOW whenever the input does not conform to
a SMPTE or DVB-ASI compliant data stream. In this case, the serial digital
loop-through output will be a buffered version of the input.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH, the serial digital output will be a reclocked version of the
input signal regardless of whether the device is in SMPTE, DVB-ASI or
Data-Through mode.
When set LOW, the serial digital output will be a buffered version of the
input signal in all modes.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1560 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Voltage Controlled Oscillator
GS1560A 制造商:Gennum Corporation 功能描述:
GS1560A_07 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer
GS1560A_09 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer
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