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參數(shù)資料
| 型號(hào)： | GS1559-CBE2 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver |
| 中文描述： | GS1559的HD - LINX進(jìn)程，商標(biāo)第二多速率解串器與環(huán)通電纜驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 6/74頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | GS1559-CBE2 |
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GS1559 Data Sheet
30572 - 4
July 2005
6 of 74
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
A1
LF
Analog
Output
Control voltage to external voltage controlled oscillator. Nominally +1.25V
DC.
A2
VCO_VCC
–
Output
Power
Power supply for the external voltage controlled oscillator. Connect to pin 7
of the GO1525. This pin is an output.
Should be isolated from all other power supplies.
A3
VCO_GND
–
Output
Power
Ground reference for the external voltage controlled oscillator. Connect to
pins 2, 4, 6, and 8 of the GO1525. This pin is an output.
Should be isolated from all other grounds.
A4, A5
VCO, VCO
Analog
Input
Differential inputs for the external VCO reference signal. For single ended
devices such as the GO1525, VCO should be AC coupled to VCO_GND.
VCO is nominally 1.485GHz.
A6, B5,
B6, C4,
C5, D2,
D3, D7,
E3, E7,
F2, F3, F7,
G2, G3,
G7, H3,
J2, J3, J4,
NC
–
–
No Connect.
A7
PCLK
–
Output
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode
PCLK = 74.25MHz or 74.25/1.001MHz
HD 10-bit mode
PCLK = 148.5MHz or 148.5/1.001MHz
SD 20-bit mode
PCLK = 13.5MHz
SD 10-bit mode
PCLK = 27MHz
A8, E8, K8
IO_VDD
–
Power
Power supply connection for digital I/O buffers. Connect to +3.3V DC
digital.
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