參數(shù)資料
型號(hào)： GS1559-CBE2
廠商： Gennum Corporation
英文描述： GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver
中文描述： GS1559的HD - LINX進(jìn)程，商標(biāo)第二多速率解串器與環(huán)通電纜驅(qū)動(dòng)器
文件頁數(shù)： 63/74頁
文件大小： 686K
代理商： GS1559-CBE2
GS1559 Data Sheet
30572 - 4
July 2005
63 of 74
As described in
Data Through Mode on page 42
, the data bus outputs will be
forced to logic LOW if the device is set to operate in master mode but cannot
identify SMPTE TRS ID or DVB-ASI sync words in the input data stream.
4.11.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GS1559 is determined by the
output data format.
Table 4-16
below lists the possible output signal formats and
their corresponding parallel clock rates. Note that DVB-ASI output will always be in
10-bit format, regardless of the setting of the 20bit/10bit pin.
Table 4-16: Parallel Data Output Format
Output Data Format
DOUT
[19:10]
DOUT
[9:0]
PCLK
Status / Control Signals*
20bit/
10bit
SD/HD
SMPTE_BYPASS
DVB_ASI
SMPTE MODE
20bit DEMULTIPLEXED SD
LUMA
CHROMA
13.5MHz
HIGH
HIGH
HIGH
LOW
10bit MULTIPLEXED SD
LUMA /
CHROMA
FORCED
LOW
27MHz
LOW
HIGH
HIGH
LOW
20bit DEMULTIPLEXED HD
LUMA
CHROMA
74.25 or
74.25/
1.001MHz
HIGH
LOW
HIGH
LOW
10bit MULTIPLEXED HD
LUMA /
CHROMA
FORCED
LOW
148.5 or
148.5/
1.001MHz
LOW
LOW
HIGH
LOW
DVB-ASI MODE
10bit DVB-ASI
DVB-ASI
DATA
FORCED
LOW
27MHz
HIGH
HIGH
LOW
HIGH
DVB-ASI
DATA
FORCED
LOW
27MHz
LOW
HIGH
LOW
HIGH
DATA-THROUGH MODE**
20bit DEMULTIPLEXED SD
DATA
DATA
13.5MHz
HIGH
HIGH
LOW
LOW
10bit MULTIPLEXED SD
DATA
FORCED
LOW
27MHz
LOW
HIGH
LOW
LOW
20bit DEMULTIPLEXED HD
DATA
DATA
74.25 or
74.25/
1.001MHz
HIGH
LOW
LOW
LOW
10bit MULTIPLEXED HD
DATA
FORCED
LOW
148.5 or
148.5/
1.001MHz
LOW
LOW
LOW
LOW
*NOTE1: Recall that SD/HD, SMPTE_BYPASS, and DVB_ASI are input control pins in slave mode to be set by the application layer, but are
output status signals set by the device in master mode.
**NOTE 2: Data-Through mode is only available in slave mode
Data Through Mode on page 42
.
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