GS1559 Data Sheet
30572 - 4
July 2005
57 of 74
4.10.6 Error Correction and Insertion
In addition to signal error detection and indication, the GS1559 may also correct
certain types of errors by inserting corrected code words, checksums and CRC
values into the data stream. These features are only available in SMPTE mode and
IOPROC_EN/
DIS
must be set HIGH. Individual correction features may be enabled
or disabled via the IOPROC_DISABLE register (
Table 4-14
).
All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling
all of the processing features. To disable any individual error correction feature, the
host interface must set the corresponding bit HIGH in the IOPROC_DISABLE
register.
Table 4-14: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
Description
R/W
Default
IOPROC_DISABLE
Address: 000h
15-9
–
Not Used.
–
–
8
H_CONFIG
Horizontal sync timing output configuration. Set
LOW for active line blanking timing. Set HIGH for H
blanking based on the H bit setting of the TRS
words. See
Figure 4-2
.
0
7-6
–
Not Used.
–
–
5
ILLEGAL_REMAP
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable.
The IOPROC_EN/DIS pin must be set HIGH.
R/W
0
4
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical
Redundancy Check (CRC) error correction
insertion. In SD mode set HIGH to disable. The
IOPROC_EN/DIS pin must be set HIGH.
R/W
0
3
ANC_CSUM_INS
Ancillary Data Check-sum insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set
HIGH.
R/W
0
2
CRC_INS
Y and C line based CRC insertion. In HD mode,
inserts line based CRC words in both the Y and C
channels. Set HIGH to disable. The
IOPROC_EN/DIS pin must be set HIGH.
R/W
0
1
LNUM_INS
Y and C line number insertion. In HD mode set
HIGH to disable. The IOPROC_EN/DIS pin must be
set HIGH.
R/W
0
0
TRS_INS
Timing Reference Signal Insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set
HIGH.
R/W
0