參數(shù)資料
型號(hào): GM72V66841ET-7
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM
中文描述: 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, TSOP2-54
文件頁(yè)數(shù): 5/57頁(yè)
文件大小: 592K
代理商: GM72V66841ET-7
LG Semicon
GM72V66841CT/CLT
Command Operation
Command Truth Table
The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE
and address pins.
* Notes : H: V
IH
, L: V
IL
, X: V
IH
or V
IL
, V: Valid address input
Function
Ignore command
Symbol
CKE
n-1
No Operation
Burst stop in full page
Column address and
read command
Read with auto-Precharge
Write with auto-Precharge
Row address strobe and
bank active
Precharge all banks
Column address and
write command
CS
RAS
CAS
WE
A12~
A13
A10
A0~
A11
DESL
NOP
BST
READ
READ A
WRIT
WRIT A
ACTV
PALL
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
V
H
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
X
H
H
L
L
L
L
H
H
L
X
H
L
H
H
L
L
H
L
H
X
X
X
V
V
V
V
V
X
X
X
X
X
L
H
L
H
V
H
X
X
X
X
V
V
V
V
V
X
X
n
H
X
L
L
L
L
V
V
V
Mode register set
MRS
Refresh
REF/SELF
Precharge select bank
PRE
H
X
L
L
H
L
V
L
X
4
V
SS
and V
SSQ
(Power supply pins)
Ground is connected. (V
SS
is for the internal circuit and V
SSQ
is for the output
buffer.)
NC
No Connection pins.
DESCRIPTION
Pin Name
V
CC
and V
CCQ
(Power supply pins)
3.3 V is applied. (V
CC
is for the internal circuit and V
CCQ
is for the output
buffer.)
DQ0 ~ DQ7
(I/O pins)
Data is input and output from these pins. These pins are the same as those of a
conventional DRAM.
Pin Description(Continued)
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