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參數(shù)資料
| 型號： | GM72V66841ET-7 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, TSOP2-54 |
| 文件頁數(shù)： | 35/57頁 |
| 文件大?。?/td> | 592K |
| 代理商： | GM72V66841ET-7 |
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LG Semicon
GM72V66841CT/CLT
Mode Register Set to Bank-Active Command
Interval :
The interval between setting the mode
register and executing a bank-active command
must be no less than
t
RSA
.
34
CLK
Command
t
RSA
Address
(A0-A13)
Mode
Register Set
Bank
Active
MRS
ACTV
CODE
BS & ROW
DQM Control
(GM72V661641CT/CLT)
The DQMU and DQML mask the upper and
lower bytes of DQ data, respectively. The timing
of DQMU/DQML is different during reading and
writing.
Reading:
When data is read, the output buffer
can be controlled by DQMU/DQML. By setting
DQMU/DQML to Low, the output buffer
becomes Low-Z, enabling data output. By setting
DQMU/DQML to High, the output buffer
becomes High-Z, and the corresponding data is
not output. However, internal reading operations
continue. The latency of DQMU/DQML during
reading is 2.
DQM Control
(
GM72V66841CT/CLT,GM72V66441CT
)
The DQM mask DQ data. The timing of DQM is
different during reading and writing.
Reading:
When data is read, the output buffer
can be controlled by DQM. By setting DQM to
Low, the output buffer becomes Low-Z, enabling
data output. By setting DQM to High, the output
buffer becomes High-Z, and the corresponding
data is not output. However, internal reading
operations continue. The latency of DQM during
reading is 2.
Writing:
Input data can be masked by DQM. By
setting DQM to Low, data can be written. In
addition, when DQM is set to High, the
corresponding data is not written, and the
previous data is held. The latency of DQM during
writing is 0.
Writing:
Input data can be masked by
DQMU/DQML. By setting DQMU/DQML to
Low, data can be written. In addition, when
DQMU/DQML is set to High, the corresponding
data is not written, and the previous data is held.
The latency of DQMU/DQML during writing
is 0.
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| GM72V66841ET-7K | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GM72V66841ET-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| GM72V66841ET-7J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| GM72V66841ET-7K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| GM72V66841EXX | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
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