參數(shù)資料
型號: GL9701-MXG
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM to PCI Bridge
中文描述: 的PCI ExpressTM到PCI橋
文件頁數(shù): 58/75頁
文件大?。?/td> 1077K
代理商: GL9701-MXG
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 58
0
RWS
0
Receiver Error Mask
6
RWS
0
Bad TLP Mask
7
RWS
0
Bad DLLP Mask
8
RWS
0
REPLAY_NUM Rollover Mask
12
RWS
0
Replay Timer Timeout Mask
6.49 Offset 118h: Advanced Error Capabilities and Control Register
Bits
Type
Default
Description
4:0
ROS
00h
First Error Pointer
Identifies the bit position of the first error
reported in the Uncorrectable Error Status register.
5
RO
1b
ECRC Generation Capable
This bit indicates that
the device is capable of generating ECRC.
6
RWS
0b
ECRC Generation Enable
This bit when set
enables ECRC generation.
7
RO
1b
ECRC Check Capable
This bit indicates that the
device is capable of checking ECRC.
8
RWS
0b
ECRC Check Enable
This bit when set enables
ECRC checking.
6.50 Offset 11ch: Header Log Register
Bits
Type
Default
Description
127:0
ROS
0h
Header Log
Header of TLP associated with error
6.51 Offset 12ch: Secondary Uncorrectable Error Status Register
Bits
Type
Default
Description
0
RW1CS
0
Target-Abort on Split Completion Status
1
RW1CS
0
Master-Abort on Split Completion Status
2
RW1CS
0
Received Target-Abort Status
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