參數(shù)資料
型號(hào)： GL9701-MXG
廠(chǎng)商： Genesys Logic, Inc.
英文描述： PCI ExpressTM to PCI Bridge
中文描述： 的PCI ExpressTM到PCI橋
文件頁(yè)數(shù)： 40/75頁(yè)
文件大小： 1077K
代理商： GL9701-MXG
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 40
to 0, indicating support for 16-bit I/O addressing only.
7:4
RW
0h
I/O Base Address Bits [15:12]:
These bits define the bottom
address of an address range to determine when to forward I/O
transactions from one interface to another.
These bits correspond to address lines[15:12] for 4 KB alignment.
Bits[11:0] are assumed to be 000h.
11:8
RO
0h
I/O Limit Addressing Capability (IOLC):
Each of these bits is
hard-wired to 0, indicating support for 16-bit I/O addressing only.
15:12
RW
0h
I/O Limit Address Bits [15:12] (IOLA):
These bits define the top
address of an address range to determine when to forward I/O
transactions from PCI Express* to PCI. These bits correspond to
address lines[15:12] for 4 KB aligned window. Bits[11:0] are
assumed to be FFFh.
6.17 Offset 1eh: Secondary Status Register
Bits
Type
Default
Description
4:0
RsvdZ
00h
Reserved
5
RO
1b
66 MHz Capable:
This bit indicates that the secondary interface
of the bridge is 66 MHz-capable.
6
RsvdZ
0b
Reserved
7
RO
0b
Fast Back-to-Back Transactions Capable:
This bit indicates that
the secondary interface is not able to receive fast back-to-back
cycles.
8
RW1C
0b
Master Data Parity Error
–
This bit is used to report the
detection of an uncorrectable data error by the bridge. This bit is
set if the bridge is the bus master of the transaction on the
secondary interface, the Parity Error Response Enable bit in the
Bridge Control register is set, and either of the following two
conditions occur:
The bridge asserts PERR# on a read transaction.
The bridge detects PERR# asserted on a write transaction.
Once set, this bit remains set until it is reset by writing a 1 to this
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