參數(shù)資料
型號(hào)： GL9701-MXG
廠商： Genesys Logic, Inc.
英文描述： PCI ExpressTM to PCI Bridge
中文描述： 的PCI ExpressTM到PCI橋
文件頁數(shù)： 39/75頁
文件大?。?/td> 1077K
代理商： GL9701-MXG
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 39
6.12 Offset 18h: Primary Bus Number Register
Bits
Type
Default
Description
7:0
RW
00h
Primary Bus Number:
Used to record the Bus Number of the
logical PCI bus segment to which the primary interface of the
bridge is connected. Configuration software is required to program
the value into this register..
6.13 Offset 19h: Secondary Bus Number Register
Bits
Type
Default
Description
7:0
RW
00h
Secondary Bus Number:
Used to record the Bus Number of the
PCI bus segment to which the secondary interface of the bridge is
connected. Configuration software programs the value in this
register.
6.14 Offset 1ah: Subordinate Bus Number Register
Bits
Type
Default
Description
7:0
RW
00h
Subordinate Bus Number:
Used to record the Bus Number of the
highest numbered PCI bus segment which is downstream of (or
subordinate to) the bridge. Configuration software programs the
value in this register.
6.15 Offset 1bh: Secondary Latency Timer Register
Bits
Type
Default
Description
7:0
RW
00h
Secondary Latency Timer:
This register specifies, in units of PCI
bus clocks, the value of the Latency Timer for the secondary
interface GL9701.
6.16 Offset 1ch: IO Base and IO Limit Register
Bits
Type
Default
Description
3:0
RO
0h
I/O Base Addressing Capability:
Each of these bits is hard-wired
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