參數(shù)資料
型號: GL9701-MXG
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM to PCI Bridge
中文描述: 的PCI ExpressTM到PCI橋
文件頁數(shù): 49/75頁
文件大?。?/td> 1077K
代理商: GL9701-MXG
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 49
6.29 Offset 74h: PCI Express Device Capabilities Register
Bits
Type
Default
Description
2:0
RO
010b
Max
_
Payload
_
Size Supported
512 bytes max payload size is
supported.
4:3
RO
00b
Phantom Functions Supported
No function number bits used
for Phantom Functions; device may implement all function
numbers.
5
RO
0b
Extended Tag Field Supported
5-bit Tag field supported
8:6
RO
111b
Endpoint L0s Acceptable Latency
The acceptable total latency
that an Endpoint can withstand due to the transition from L0s state
to the L0 state is more than 4
μ
s.
11:9
RO
111b
Endpoint L1 Acceptable Latency
The acceptable latency that an
Endpoint can withstand due to the transition from L1 state to the
L0 state is more than 64
μ
s.
12
RO
0b
Attention Button Present
Not supported.
13
RO
0b
Attention Indicator Present
Not supported.
14
RO
0b
Power Indicator Present
Not supported.
17:15
RsvdP
000b
RsvdP
25:18
RO
00h
Captured Slot Power Limit Value
In combination with the Slot
Power Limit Scale value, specifies the upper limit on power
supplied by slot. This value is set by the Set_Slot_Power_Limit
Message
27:26
RO
00b
Captured Slot Power Limit Scale
Specifies the scale used for
the Slot Power Limit Value. This value is set by the
Set_Slot_Power_Limit Message.
6.30 Offset 78h: PCI Express Device Control Register
Bits
Type
Default
Description
0
RW
0b
Correctable Error Reporting Enable
This bit controls
reporting of correctable errors.
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