參數(shù)資料
型號: GL9701-MXG
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM to PCI Bridge
中文描述: 的PCI ExpressTM到PCI橋
文件頁數(shù): 42/75頁
文件大?。?/td> 1077K
代理商: GL9701-MXG
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 42
15
RW1C
0b
Detected Parity Error
This bit reports the detection of an
uncorrectable address, attribute, or data error by the bridge on its
secondary interface.
The bit is set irrespective of the state of the Parity Error
Response Enable bit in the Bridge Control register.
0
Uncorrectable address, attribute, or data error not
detected on secondary interface
1
Uncorrectable address, attribute, or data error detected on
secondary interface
6.18 Offset 20h: Memory Base and Limit Register
Bits
Type
Default
Description
3:0
RO
0h
Reserved
15:4
RW
000h
Memory Base:
These bits are compared with bits[31:20] of the
incoming address to determine the lower 1 MB-aligned value
(inclusive) of the range. The incoming address must be greater
than or equal to this value.
19:16
RO
0h
Reserved
31:20
RW
000h
Memory Limit:
These bits are compared with bits[31:20] of the
incoming address to determine the upper 1 MB-aligned value
(exclusive) of the range. The incoming address must be less than
this value.
6.19 Offset 24h: Prefetchable Memory Base and Limit Register
Bits
Type
Default
Description
3:0
RO
0h
64-bit Indicator:
These bits indicate that 64-bit addressing is not
supported for the base.
15:4
RW
000h
Prefetchable Memory Base:
These bits are compared with
bits[31:20] of the incoming address to determine the lower 1
MB-aligned value (inclusive) of the range. The incoming address
must be greater than or equal to this value.
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