參數(shù)資料
型號: GL9701-MXG
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM to PCI Bridge
中文描述: 的PCI ExpressTM到PCI橋
文件頁數(shù): 17/75頁
文件大小: 1077K
代理商: GL9701-MXG
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 17
3.4.2 Secondary PCI Interface
Name
Type
Description
AD[31:0]
TS
Address/Data
CBE[3:0]_N
TS
Command/Byte Enable
FRAME_N
STS
Secondary PCI interface frame
IRDY_N
STS
Secondary PCI interface initiator ready
TRDY_N
STS
Secondary PCI interface target ready
STOP_N
STS
Secondary PCI interface stop indicator
DEVSEL_N
STS
Secondary PCI interface device select
PAR
TS
Secondary PCI interface parity
PER_N
STS
Secondary PCI interface parity error detect
SER_N
OD
Secondary PCI interface system error
PCIRST_N
O
Secondary PCI bus Reset
LOCK_N
STS
Secondary PCI interface target ready
REQ[4:0]_N
I
Requests 4-0, activated by the secondary bus masters to request the
use of the secondary bus.
REQ0_N is a dual-purpose signal. When the bridge
s internal arbiter
is enabled, this signal is used as a request input, to be activated by a
secondary bus master requesting the use of the secondary bus. When
the internal arbiter is disabled, REQ0_N is used by the bridge as its
grant input signal.
GNT[4:0]_N
O
Grants 4-0, activated by the bridge
s internal arbiter to grant usage of
the secondary bus to the master that activated the corresponding
request signal.
GNT0_N is a dual-purpose signal. When the bridge
s internal arbiter
is enabled, this signal is used as a grant output, activated by the bridge
to grant the use of the secondary bus to the master who requested the
use with the GNT0_N signal. When the internal arbiter is disabled,
this signal is used by the bridge as its request output signal.
PCICLKI
I
PCI clock input.
INTA_N,
INTB_N,
INTC_N,
I
Interrupt from secondary interface.
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