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參數(shù)資料
| 型號： | GL9701-MXG |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM to PCI Bridge |
| 中文描述： | 的PCI ExpressTM到PCI橋 |
| 文件頁數(shù)： | 34/75頁 |
| 文件大小： | 1077K |
| 代理商： | GL9701-MXG |
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GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 34
6.1 Offset 00h: Device Identification
Generic configuration software will be able to determine what devices are available on PCI bus via these
information. All of these registers are read-only.
Bits
Type
Default
Description
15:0
RO
17a0h
Vendor ID
: This field identifies the manufacturer of the device.
31:16
RO
7163
Device ID
: This field identifies the particular device.
6.2 Offset 04h: Command Register
Bits
Type
Default
Description
0
RW
0b
I/O Space:
Controls a device
’
s response to I/O Space accesses.
0
–
Disables the device response.
1
–
Allows the device torespond to I/O Space accesses.
1
RW
0b
Memory Space:
Controls a device
’
s response to Memory Space
accesses.
0
–
Disables the device response.
1
–
Allows the device to respond to Memory Space accesses.
2
RW
0b
Bus Master:
Controls a device
’
s ability to act as a master on the
PCI bus.
0
–
Disables the device from generating PCI accesses.
1
–
Allows the device to behave as a bus master.
3
RO
0b
Special Cycles
: Does not apply to PCI Express Bridge.
4
RO
0b
Memory Write and Invalidate Enable:
GL9701 does not
optionally promote Memory Write Requests to Memory Write
and Invalidate transactions on PCI.
5
RO
0b
VGA Palette Snoop
: Does not apply to PCI Express bridges.
6
RW
0b
Parity Error Response:
Controls the bridge
’
s setting of the Master Data Parity Error bit in
the Status register in response to a received poisoned TLP from
PCI Express.
0
–
Disables the setting of the Master Data Parity Error bit.
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| GL9714 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
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