參數(shù)資料
型號: GL9701-MXG
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM to PCI Bridge
中文描述: 的PCI ExpressTM到PCI橋
文件頁數(shù): 52/75頁
文件大小: 1077K
代理商: GL9701-MXG
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 52
number for the given PCI Express Link.
6.33 Offset 80h: PCI Express Link Control Register
Bits
Type
Default
Description
1:0
RO
00b
Active State Power Management (ASPM) Control
GL9701 does not support ASPM.
2
RsvdP
0b
RsvdP
3
RO
0b
Read Completion Boundary (RCB)
Indicates the RCB value
for the Root Port. Defined encodings are:
0b : 64 byte
1b : 128 byte
4
RW
0b
Link Disable
This bit disables the Link when set to 1b.
5
RW
0b
Retrain Link
A write of 1b to this bit initiates Link retraining by
directing the Physical Layer LTSSM to the Recovery state.
6
RW
0b
Common Clock Configuration
This bit when set indicates
that this component and the component at the opposite end of
this Link are operating with a distributed common reference clock.
A value of 0b indicates that this component and the component at
the opposite end of this Link are operating with asynchronous
reference clock.
7
RW
0b
Extended Synch
This bit when set forces the transmission of
4096 FTS ordered sets in the L0s state followed by a single SKP
ordered set prior to entering the L0 state, and the transmission of
1024 TS1 ordered sets in the L1 state prior to entering the
Recovery state.
15:8
RsvdP
00h
RsvdP
6.34 Offset 82h: PCI Express Link Status Register
Bits
Type
Default
Description
3:0
RO
0h
Link Speed
This field indicates the negotiated Link speed of the
given PCI Express Link.Defined encodings are:
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