參數(shù)資料
型號(hào)： GF9331-CBP
廠商： Gennum Corporation
英文描述： DTV/SDTV Motion Co-processor
中文描述： 數(shù)字電視/標(biāo)清運(yùn)動(dòng)協(xié)處理器
文件頁(yè)數(shù)： 8/31頁(yè)
文件大?。?/td> 337K
代理商： GF9331-CBP
GF9331 Data Sheet
Proprietary and Confidential
18303 - 4
June 2004
8 of 31
Tristate Leakage Current
I
TRILEAK
-
-
10
μ
A
a
Input Logic LOW Voltage
V
IL
-
-
0.8
V
a
Input Logic HIGH Voltage
V
IH
2.1
-
-
V
a
Output Logic LOW Voltage
I
OL
= 4mA
V
OL
-
0.2
0.4
V
a
Output Logic HIGH Voltage
I
OH
= -4mA
V
OH
2.7
-
-
V
a
a. Production, test and QA are performed at room temperature.
Table 2-2: DC Electrical Characteristics (Continued)
V
DDIO
= 3.0 to 3.6V, V
DDCORE
= 2.25 to 2.75V, T
A
= 0 to 70
o
C, unless otherwise shown.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Notes
Table 2-3: AC Electrical Characteristics - SDRAM Interfaces
The SDRAM 1 Interface signals include S1_CLK, S1_CS, S1_RAS, S1_CAS, S1_WE, S1_ADDR[13:0] and
S1_DAT[15:0]. The SDRAM 2 Interface signals include S2_CLK, S2_CS, S2_RAS, S2_CAS, S2_WE,
S2_ADDR[13:0] and S2_DAT[15:0].
V
DDIO
= 3.0 to 3.6V, V
DDCORE
= 2.25 to 2.75V, T
A
= 0 to 70
o
C, unless otherwise shown.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Notes
Clock Input Frequency
F
HSCI_SD
-
85
90
MHz
a
Input Data Setup Time
t
SU_SD
2.0
-
-
ns
a
,
b
Input Data Hold Time
t
IH_SD
2.5
-
-
ns
a
,
b
Input Clock Duty Cycle
40
-
60
%
a
Output Data Delay Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OD_SD
-
-
9.1
ns
a
Output Data Hold Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OH_SD
2.0
-
-
ns
a
Output Enable Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OEN_SD
-
-
20
ns
a
,
c
Output Disable Time
V
DDIO
=3.6V,
C
L
=15pF load
t
ODIS_SD
-
-
20
ns
a
,
c
Output Data Rise/Fall Time
V
DDIO
=3.6V,
C
L
=15pF load
t
ODRF_SD
-
-
2.0
ns
a
,
d
a.Based on simulation results, verified during device characterization process.
b.50% levels.
c.Two clock cycles allocated for data bus turnaround.
d.20% to 80% levels.
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