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參數(shù)資料
| 型號： | GF9331-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | DTV/SDTV Motion Co-processor |
| 中文描述： | 數(shù)字電視/標(biāo)清運(yùn)動協(xié)處理器 |
| 文件頁數(shù)： | 21/31頁 |
| 文件大?。?/td> | 337K |
| 代理商： | GF9331-CBP |
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GF9331 Data Sheet
Proprietary and Confidential
18303 - 4
June 2004
21 of 31
3.5.2.2 Parallel Write Operation
A write cycle to the parallel interface is shown in
Figure 3-11: Write Cycle to the
Parallel Interface
. First an 8-bit address word is provided to the DAT_IO port by
setting the R_W pin to LOW and A_D pin to HIGH. The MSB of the address word
contains an auto-update flag, which allows automatic configuration of predefined
registers (used during write operations only).
Figure 3-11: Write Cycle to the Parallel Interface
The 5 LSB's of the address word contain the address location for the read or write
operation. The remaining address word bits DAT_IO[6:5] are reserved. The address
word is registered on the falling edge of
CS
.
Following this, the A_D pin is driven LOW and two data words are sent upper byte (UB)
word first and are each clocked in on the falling edge of
CS
. Two 8-bit data words must
follow each address word to occupy each 16-bit parameter which are defined in
Figure
3-12: Host Interface Register Allocation
.
3.5.2.3 Parallel Read Operation
A read cycle begins with an address write by setting the R_W pin LOW and A_D
HIGH. The address is clocked on the falling edge of CS. Following the address, the
R_W pin must be driven HIGH and A_D driven LOW to allow the upper byte of data
to be clocked out on the first falling edge of CS followed by the lower byte on the
second falling edge of CS.
ADDRESS
(UB)
DATA_IN
D(LB)
ADDRESS
DA(UB)
DA(LB)
DAT_IO(7..0)
R_W
A_D
CS
tSU_HI
tIH_HI
tOEN_HI
tODIS_HI
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