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參數(shù)資料
| 型號(hào)： | GF9331-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | DTV/SDTV Motion Co-processor |
| 中文描述： | 數(shù)字電視/標(biāo)清運(yùn)動(dòng)協(xié)處理器 |
| 文件頁(yè)數(shù)： | 16/31頁(yè) |
| 文件大?。?/td> | 337K |
| 代理商： | GF9331-CBP |
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GF9331 Data Sheet
Proprietary and Confidential
18303 - 4
June 2004
16 of 31
3.4 Seamless Interface to External SDRAMs
The GF9331 requires two independent external field buffers, each implemented
with a 1Mx16-bit (min) SDRAM configuration. This configuration supports all
operational modes.
3.5 Host Interface
The GF9331 provides both serial and parallel host interface control ports for the
configuration of internal parameters. The GF9331 is also able to operate in
stand-alone mode, with no host interface control. In stand-alone mode, the video
standard STD[4:0] and mode of operation MODE (pins or registers, depending on
the HOST_EN state). These values are loaded into the device on a falling transition
of HOST_EN or after setting RESET LOW.
Both the serial and parallel interfaces share common pins as described in
Table
3-4: Host Interface Common Pins
.
Table 3-3: SDRAM Configuration
Format
Bypass
Configuration
per Bank
a
Total of
ADDR and
BANK
b
SDRAM properties (per bank)
Recomended
Min.
Freq.
(MHz)
Min.
Access
Time
(ns)
CAS
Latency
SD
Yes
1(1Mx16)
12
90
5.5
3
Micron:
MT48LC4M16A2,
MT48LC8M16A2
No
1(1Mx16)
12
90
5.5
3
HD
Yes
1(1Mx16)
12
90
5.5
3
No
1(1Mx16)
12
90
5.5
3
a.There are 2.
b.This is assuming a 8-column structure.
Table 3-4: Host Interface Common Pins
GF9331 Pin Name
Parallel Mode
Serial Mode
CS
CHIP select
SCLK - Serial Clock
DAT_IO[0]
Data/address (bit 0)
SDI - Serial data in
DAT_IO[1]
Data/address (bit 1)
(not used)
DAT_IO[2]
Data/address (bit 2)
(not used)
DAT_IO[3]
Data/address (bit 3)
(not used)
DAT_IO[4]
Data/address (bit 4)
(not used)
DAT_IO[5]
Data/address (bit 5)
(not used)
DAT_IO[6]
Data/address (bit 6)
(not used)
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