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參數(shù)資料
| 型號： | GF9331-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | DTV/SDTV Motion Co-processor |
| 中文描述： | 數(shù)字電視/標(biāo)清運(yùn)動(dòng)協(xié)處理器 |
| 文件頁數(shù)： | 20/31頁 |
| 文件大小： | 337K |
| 代理商： | GF9331-CBP |
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GF9331 Data Sheet
Proprietary and Confidential
18303 - 4
June 2004
20 of 31
3.5.2 Host Interface Parallel Mode
The Gennum Parallel Peripheral Interface (GPPI) consists of an 8-bit multiplexed
address/data bus (DATA_IO[7:0]), a chip select pin (CS), a read/write pin (R_W),
and an address/data pin (A_D) as shown in
Figure 3-9: Host Interface Parallel
Mode
.
Figure 3-9: Host Interface Parallel Mode
Data is strobed in/out of the parallel interface on the falling edge of
CS
. The GF9331
drives the DAT_IO[7:0] bus when the R_W pin is HIGH and the
CS
pin is LOW,
otherwise this port is in a high impedance state.
3.5.2.1 Parallel Address Word Description
The 8-bit address word loads in the address to be accessed and allows the
Auto-Configure bit to be set. The MSB is the Auto-Configure bit, followed by two
reserved bits and a 5-bit address as shown in
Figure 3-10: Parallel Address Word
Bit Representation
.
Figure 3-10: Parallel Address Word Bit Representation
A_D
CS
ADDR/DATA (DAT_IO[7:0])
R_W
SLAVE (GF9331)
uC_A/D
uC_CS
uC_ADDR/DATA
uC_R/W
MASTER (uC)
AC
RSV
RSV
A4
A0
A1
A3
A2
MSB
LSB
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