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參數(shù)資料
| 型號： | GF9331-CBP |
| 廠商： | Gennum Corporation |
| 英文描述： | DTV/SDTV Motion Co-processor |
| 中文描述： | 數(shù)字電視/標清運動協(xié)處理器 |
| 文件頁數(shù)： | 4/31頁 |
| 文件大?。?/td> | 337K |
| 代理商： | GF9331-CBP |
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GF9331 Data Sheet
Proprietary and Confidential
18303 - 4
June 2004
4 of 31
Table 1-1: Pin Descriptions
Symbol
Pin Grid
Type
Description
RESET
A1
I
Active low, asynchronous RESET. Resets all internal logic to default
conditions. Should be applied on power up.
VCLK_IN
F1
I
Video input clock. When the input is SDTV the input clock will be 27, 36, 54 or
72MHz. When the input format is HDTV, the input clock will be 74.25 or
74.25/1.001MHz.
MEMCLK_IN
H1
I
Memory clock for SDRAM operation when VLCK_IN > 36MHz. 90MHz input
(supplied by an off-chip crystal oscillator).
Y_IN[9:0]
B1, C1, C2, C3, D1, D2,
D3, E1, E2, E3
I
8/10-bit input data bus for separate luminance or multiplexed luminance and
colour difference video data. When supplying 8-bit data to the GF9331,
Y_IN[1:0] will be set LOW and the 8-bit data supplied to Y_IN[9:2].
C_IN[9:0]
J3, J4, K1, K2, K3, K4, L4,
L3, L2, L1
I
8/10-bit input data bus for colour difference video data. When supplying 8-bit
data to the GF9331, C_IN[1:0] will be set LOW and the 8-bit data supplied to
C_IN[9:2].
F_IN
N2
I
Video timing control. F_IN identifies the ODD and EVEN fields in the incoming
video signal. F_IN will be LOW in Field 1 and HIGH in Field 2.
V_IN
N3
I
Video timing control. V_IN represents the vertical blanking signal associated
with the incoming video signal. V_IN is HIGH during the vertical blanking
interval and LOW during active video.
H_IN
N4
I
Video timing control. H_IN represents the horizontal blanking signal
associated with the incoming video signal. H_IN is HIGH during horizontal
blanking and LOW during active video.
FVH_EN
N1
I
Control signal input. When HIGH, the F_IN, V_IN, and H_IN input pins will be
used for video data signalling. When LOW, embedded TRS’s will be detected
for video data signalling.
VM_MODE
M2
I
Control signal input. When HIGH, the vertical motion detection is enabled.
ED_MODE
M1
I
Control signal input. When HIGH, the edge direction detection is enabled.
STD[4:0]
G2, G3, G4, H2, H3
I
Video format definition. Defines the video standard when operating without the
host interface. See
Table 3-1: Encoding of STD[4:0] for Selecting Input Data
Format
. STD[4:0] is read into the device on a falling transition of HOST_EN or
after a RESET.
MODE
F3
I
Operating mode selection. When HIGH, the GF9331 motion co-processing is
enabled. When LOW, the GF9331 motion co-processing is bypassed. See
Modes of Operation
. MODE is read into the device on a falling transition of
HOST_EN or after a RESET.
HOST_EN
E4
I
Host interface enable. When set HIGH, the GF9331 is configured through the
host interface. When set LOW, the GF9331 is manually configured via input
pins. These values are loaded in on the falling transition of HOST_EN.
SER_MD
G1
I
Host interface mode selection. Enables serial mode operation when HIGH.
Enables parallel mode operation when LOW.
CS
P2
I
Functions as an active low chip select input for host interface parallel mode
operation. Functions as a serial clock input for host interface serial mode
operation.
DAT_IO[7:0]
R4, R3, R2, R1, T4, T3,
T2, T1
I/O
Host interface bi-directional data bus for parallel mode. In serial mode,
DAT_IO[7] serves as the serial data output pin and DAT_IO[0] serves as the
serial data input pin.
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