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參數(shù)資料
| 型號： | EVAL-AD7193EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR AD7193 |
| 設計資源： | EVAL-AD7193 Schematic AD7193 Gerber Files |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7193 |
| 已供物品： | 板，線纜 |
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Data Sheet
AD7193
Rev. D | Page 47 of 56
CHOP ENABLED (SINC3 FILTER)
With chop enabled, the ADC offset and offset drift are minimized.
The analog input pins are continuously swapped. With the analog
input pins connected in one direction, the settling time of the
sinc filter is allowed and a conversion is recorded. The analog
input pins invert and another settled conversion is obtained.
Subsequent conversions are averaged to minimize the offset.
This continuous swapping of the analog input pins and the
averaging of subsequent conversions means that the offset drift
is also minimized. With chop enabled, the resolution increases
by 0.5 bits. Using the sinc3 filter with chop enabled is suitable
for output data rates up to 320 Hz.
SINC3/SINC4
POST FILTER
MODULATOR
ADC
CHOP
083
67
-045
Figure 49. Chop Enabled (Sinc3 Chop Enabled)
Output Data Rate and Settling Time (Sinc3 Chop Enabled)
For the sinc3 filter, the output data rate is equal to
fADC = fCLK/(3 × 1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The value of FS[9:0] can be varied from 1 to 1023. This results
in an output data rate of 1.56 Hz to 1600 Hz. The settling time is
equal to
tSETTLE = 2/fADC
Table 33. Examples of Output Data Rates and the
Corresponding Settling Time (Chop Enabled, Sinc3 Filter)
FS[9:0]
Output Data Rate (Hz)
Settling Time (ms)
96
16.7
120
80
20
100
When a channel change occurs, the modulator and filter are reset.
The complete settling time is required to generate the first
conversion after the channel change. Subsequent conversions
on this channel occur at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
CH B
0
83
67
-0
46
Figure 50. Channel Change (Sinc3 Chop Enable)
If conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input; therefore, it continues to output conversions at the
programmed output data rate. However, it is at least two
conversions later before the output data accurately reflects
the analog input. If the step change occurs while the ADC is
processing a conversion, then the ADC takes three conversions
after the step change to generate a fully settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
0
836
7-
0
47
Figure 51. Asynchronous Step Change in Analog Input (Sinc3 Chop Enabled)
The cutoff frequency f3dB is equal to
f3dB = 0.24 × fADC
50 Hz/60 Hz Rejection (Sinc3 Chop Enabled)
When FS[9:0] is set to 96 and chopping is enabled, the filter
response shown in Figure 52 is obtained. The output data rate
is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping
introduces notches at odd integer multiples of fADC/2. The notches
due to the sinc filter in addition to the notches introduced by
the chopping means that simultaneous 50 Hz and 60 Hz rejection
is achieved for an output data rate of 16.7 Hz. The rejection at
50 Hz/60 Hz ± 1 Hz is typically 53 dB, assuming a stable
master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
FIL
T
E
R
GA
IN
(
d
B
)
08
36
7-
0
48
Figure 52. Sinc3 Filter Response (FS[9:0] = 96, Chop Enabled)
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