參數(shù)資料
型號： EVAL-AD7193EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 27/57頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR AD7193
設(shè)計資源： EVAL-AD7193 Schematic
AD7193 Gerber Files
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7193
已供物品： 板，線纜
AD7193
Data Sheet
Rev. D | Page 32 of 56
ANALOG INPUT CHANNEL
The AD7193 has four differential/eight pseudo differential analog
input channels that can be buffered or unbuffered. In buffered
mode (the BUF bit in the configuration register is set to 1), the
input channel feeds into a high impedance input stage of the
buffer amplifier. Therefore, the input can tolerate significant
source impedances and is tailored for direct connection to
external resistive type sensors such as strain gages or resistance
temperature detectors (RTDs).
When BUF = 0, the part operates in unbuffered mode. This
results in a higher analog input current. Note that this unbuffered
input path provides a dynamic load to the driving source.
Therefore, resistor/capacitor combinations on the input pins
can cause gain errors, depending on the output impedance of
the source that is driving the ADC input. Table 26 shows the
allowable external resistance/capacitance values for unbuffered
mode at a gain of 1 such that no gain error at the 20-bit level is
introduced.
Table 26. External RC Combination for No 20-Bit Gain Error
C (pF)
R ()
50
1.4 k
100
850
500
300
1000
230
5000
30
The absolute input voltage range in buffered mode is restricted
to a range between AGND + 250 mV and AVDD 250 mV. Care
must be taken in setting up the common-mode voltage to not
exceed these limits; otherwise, linearity and noise performance
degrade.
The absolute input voltage in unbuffered mode includes the
range between AGND 50 mV and AVDD + 50 mV. The
negative absolute input voltage limit allows the possibility of
monitoring small true bipolar signals with respect to AGND.
PROGRAMMABLE GAIN ARRAY (PGA)
When the gain stage is enabled, the output from the buffer is
applied to the input of the PGA. The presence of the PGA means
that signals of small amplitude can be gained within the AD7193
and still maintain excellent noise performance. For example, when
the gain is set to 128, the rms noise is 11 nV, typically, when the
output data rate is 4.7 Hz, which is equivalent to 22.7 bits of
effective resolution or 20 bits of noise free resolution.
The AD7193 can be programmed to have a gain of 1, 8, 16, 32,
64, or 128 by using Bit G2 to Bit G0 in the configuration register.
Therefore, with an external 2.5 V reference, the unipolar ranges
are from 0 mV to 19.53 mV to 0 V to 2.5 V, and the bipolar ranges
are from ±19.53 mV to ±2.5 V.
The analog input range must be limited to ±(AVDD 1.25 V)/gain
because the PGA requires some headroom. Therefore, if VREF =
AVDD = 5 V, the maximum analog input that can be applied to the
AD7193 is 0 V to 3.75 V/gain in unipolar mode or ±3.75 V/gain
in bipolar mode.
REFERENCE
The ADC has a fully differential input capability for the refer-
ence channel. In addition, the user has the option of selecting
one of two external reference options (REFIN1(±) or REFIN2(±)).
The reference source for the AD7193 is selected using the REFSEL
bit in the configuration register. The REFIN2(±) pins are dual
purpose: they can function as two general-purpose output pins
or as reference pins. When the REFSEL bit is set to 1, these pins
automatically function as reference pins.
The common-mode range for these differential inputs is from
AGND to AVDD. The reference voltage REFIN (REFINx(+)
REFINx()) is AVDD nominal, but the AD7193 is functional
with reference voltages from 1 V to AVDD. In applications where
the excitation (voltage or current) for the transducer on the
analog input also drives the reference voltage for the part, the
effect of the low frequency noise in the excitation source is removed
because the application is ratiometric. If the AD7193 is used in a
nonratiometric application, a low noise reference should be used.
The reference input is unbuffered; therefore, excessive RC
source impedances introduce gain errors. RC values similar to
those in Table 26 are recommended for the reference inputs.
Deriving the reference input voltage from an external resistor
means that the reference input sees significant external source
impedance. External decoupling on the REFINx pins is not
recommended in this type of circuit configuration. Conversely,
if large decoupling capacitors are used on the reference inputs,
there should be no resistors in series with the reference inputs.
Recommended 2.5 V reference voltage sources for the AD7193
include the ADR421 and ADR431, which are low noise references.
These references tolerate decoupling capacitors on REFINx(+)
without introducing gain errors in the system. Figure 23 shows the
recommended connections between the ADR421 and the AD7193.
4
2
0.1F
AVDD
ADR421
AD7193
VIN
GND
REFINx(+)
REFINx(–)
VOUT
TRIM
10F
4.7F
6
5
08367-
124
Figure 23. ADR421 to AD7193 Connections
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