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| 型號： | EVAL-AD7193EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/57頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR AD7193 |
| 設(shè)計資源： | EVAL-AD7193 Schematic AD7193 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7193 |
| 已供物品： | 板，線纜 |
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Data Sheet
AD7193
Rev. D | Page 39 of 56
TEMPERATURE SENSOR
Embedded in the AD7193 is a temperature sensor. This is selected
using the TEMP bit in the configuration register. When the
TEMP bit is set to 1, the temperature sensor is enabled. When
the temperature sensor is selected and bipolar mode is selected,
the device should return a code of 0x800000 when the temperature
is 0 Kelvin, theoretically. A one-point calibration is needed to
obtain the optimum performance from the sensor. Therefore, a
conversion at 25°C should be recorded and the sensitivity
calculated. The sensitivity is 2815 codes/°C, approximately.
The equation for the temperature sensor is
Temperature (K) = (Conversion 0x800000)/2815 K
Temperature (°C) = Temperature (K) 273
Following the one-point calibration, the internal temperature
sensor has an accuracy of ±2°C, typically.
LOGIC OUTPUTS
The AD7193 has four general-purpose digital outputs: P0, P1,
P2, and P3. These are enabled using the GP32EN and GP10EN
bits in the GPOCON register. The pins can be pulled high or
low using the P0DAT to P3DAT bits in the GPOCON register;
that is, the value at the pin is determined by the setting of the
P0DAT to P3DAT bits. The logic levels for these pins are deter-
mined by AVDD rather than by DVDD. When the GPOCON
register is read, Bit P0DAT to Bit P3DAT reflect the actual
value at the pins; this is useful for short-circuit detection.
These pins can be used to drive external circuitry, for example,
an external multiplexer. If an external multiplexer is used to
increase the channel count, the multiplexer logic pins can be
controlled via the AD7193 general-purpose output pins. The
general-purpose output pins can be used to select the active
multiplexer pin. Because the operation of the multiplexer is
independent of the AD7193, the AD7193 modulator and filter
should be reset using the SYNC pin or by a write to the mode or
configuration register each time that the multiplexer channel is
changed.
CALIBRATION
The AD7193 provides four calibration modes that can be
programmed via the mode bits in the mode register. These
modes are internal zero-scale calibration, internal full-scale
calibration, system zero-scale calibration, and system full-scale
calibration. A calibration can be performed at any time by setting
the MD2 to MD0 bits in the mode register appropriately. A
calibration should be performed when the gain is changed.
After each conversion, the ADC conversion result is scaled
using the ADC calibration registers before being written to the
data register. The offset calibration coefficient is subtracted from
the result prior to multiplication by the full-scale coefficient.
To start a calibration, write the relevant value to the MD2 to
MD0 bits. The DOUT/RDY pin and the RDY bit in the status
register go high when the calibration initiates. When the
calibration is complete, the contents of the corresponding
calibration registers are updated, the RDY bit in the status
register is reset, the DOUT/RDY pin returns low (if CS is low),
and the AD7193 reverts to idle mode.
During an internal zero-scale or full-scale calibration, the
respective zero input and full-scale input are automatically
connected internally to the ADC input pins. A system calibration,
however, expects the system zero-scale and system full-scale
voltages to be applied to the ADC pins before initiating the
calibration mode. In this way, errors external to the ADC
are removed.
From an operational point of view, treat a calibration like another
ADC conversion. A zero-scale calibration, if required, must
always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the DOUT/RDY pin to determine the end of calibration via a
polling sequence or an interrupt-driven routine.
With chop disabled, both an internal zero-scale calibration and
a system zero-scale calibration require a time equal to the settling
time, tSETTLE (4/fADC for the sinc4 filter and 3/fADC for the sinc3 filter).
With chop enabled, an internal zero-scale calibration is not
needed because the ADC itself minimizes the offset continuously.
However, if an internal zero-scale calibration is performed, the
settling time, tSETTLE (2/fADC), is required to perform the calibration.
Similarly, a system zero-scale calibration requires a time of tSETTLE
to complete.
To perform an internal full-scale calibration, a full-scale input
voltage is automatically connected to the selected analog input
for this calibration. For a gain of 1, the time required for an
internal full-scale calibration is equal to tSETTLE. For higher gains,
the internal full-scale calibration requires a time of 2 × tSETTLE.
A full-scale calibration is recommended each time the gain of a
channel is changed to minimize the full-scale error.
A system full-scale calibration requires a time of tSETTLE. With
chop disabled, the zero-scale calibration (internal or system
zero-scale) should be performed before the system full-scale
calibration is initiated.
An internal zero-scale calibration, system zero-scale calibration,
and system full-scale calibration can be performed at any output
data rate. An internal full-scale calibration can be performed at
any output data rate for which the filter word, FS[9:0], is divisible
by 16, FS[9:0] being the decimal equivalent of the 10-bit word
written to Bit FS9 to Bit FS0 in the mode register. Therefore,
internal full-scale calibrations can be performed at output data
rates such as 10 Hz or 50 Hz when chop is disabled. Using these
lower output data rates, results in better calibration accuracy.
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