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參數(shù)資料
| 型號(hào)： | EVAL-AD7193EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR AD7193 |
| 設(shè)計(jì)資源： | EVAL-AD7193 Schematic AD7193 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7193 |
| 已供物品： | 板，線纜 |
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AD7193
Data Sheet
Rev. D | Page 38 of 56
RESET
The circuitry and serial interface of the AD7193 can be reset
by writing consecutive 1s to the device; 40 consecutive 1s are
required to perform the reset. This resets the logic, the digital
filter, and the analog modulator, whereas all on-chip registers
are reset to their default values. A reset is automatically performed
on power-up. When a reset is initiated, the user must allow a
period of 500 s before accessing any of the on-chip registers. A
reset is useful if the serial interface loses synchronization due to
noise on the SCLK line.
SYSTEM SYNCHRONIZATION
The SYNC input allows the user to reset the modulator and the
digital filter without affecting any of the setup conditions on the
part. This allows the user to start gathering samples of the analog
input from a known point in time, that is, the rising edge of
SYNC. SYNC needs to be taken low for at least four master
clock cycles to implement the synchronization function.
If multiple AD7193 devices are operated from a common master
clock, they can be synchronized so that their data registers are
updated simultaneously. A falling edge on the SYNC pin resets
the digital filter and the analog modulator and places the AD7193
into a consistent, known state. While the SYNC pin is low, the
AD7193 is maintained in this state. On the SYNC rising edge,
the modulator and filter are taken out of this reset state and,
on the next clock edge, the part starts to gather input samples
again. In a system using multiple AD7193 devices, a common
signal to their SYNC pins synchronizes their operation. This
is normally done after each AD7193 has performed its own
calibration or has calibration coefficients loaded into its
calibration registers. The conversions from the AD7193s
are then synchronized.
The part is taken out of reset on the master clock falling edge
following the SYNC low-to-high transition. Therefore, when
multiple devices are being synchronized, the SYNC pin should
be taken high on the master clock rising edge to ensure that all
devices begin sampling on the master clock falling edge. If the
SYNC pin is not taken high in sufficient time, it is possible to
have a difference of one master clock cycle between the devices;
that is, the instant at which conversions are available differs
from part to part by a maximum of one master clock cycle.
The SYNC pin can also be used as a start conversion command.
In this mode, the rising edge of SYNC starts conversion, and the
falling edge of RDY indicates when the conversion is complete.
The settling time of the filter has to be allowed for each data
register update. For example, if the ADC is configured to use the
sinc4 filter, zero latency is disabled, and chop is disabled, the
settling time equals 4/fADC, where fADC is the output data rate
when continuously converting on a single channel.
ENABLE PARITY
When the ENPAR bit in the mode register is set to 1, parity is
enabled. The contents of the status register must be transmitted
along with each 24-bit conversion when the parity function is
enabled. To append the contents of the status register to each
conversion read, the DAT_STA bit in the mode register should
be set to 1. For each conversion read, the parity bit in the status
register is programmed so that the overall number of 1s trans-
mitted in the 24-bit data-word is even. Therefore, for example,
if the 24-bit conversion contains 11 ones (binary format), the
parity bit is set to 1 so that the total number of 1s in the serial
transmission is even. If the microprocessor receives an odd
number of 1s, it knows that the data received has been corrupted.
The parity function does not ensure that all errors are detected.
For example, two bits of corrupt data can result in the micro-
processor receiving an even number of 1s. Therefore, an error
condition is not detected.
CLOCK
The AD7193 includes an internal 4.92 MHz clock on chip. This
internal clock has a tolerance of ±4%. Either the internal clock
or an external crystal/clock can be used as the clock source to
the AD7193. The clock source is selected using the CLK1 and
CLK0 bits in the mode register. When an external crystal is used,
it must be connected across the MCLK1 and MCLK2 pins.
The crystal manufacturer recommends the load capacitances
required for the crystal. The MCLK1 and MCLK2 pins of the
AD7193 have a capacitance of 15 pF, typically. If an external
clock source is used, the clock source must be connected to the
MCLK2 pin, and the MCLK1 pin can remain floating.
The internal clock can also be made available at the MCLK2
pin. This is useful when several ADCs are used in an application
and the devices must be synchronized. The internal clock from
one device can be used as the clock source for all ADCs in the
system. Using a common clock, the devices can be synchronized
by applying a common reset to all devices, or the SYNC pin can
be pulsed.
BRIDGE POWER-DOWN SWITCH
In bridge applications such as strain gages and load cells, the
bridge itself consumes the majority of the current in the system.
For example, a 350 Ω load cell requires 15 mA of current when
excited with a 5 V supply. To minimize the current consumption
of the system, the bridge can be disconnected (when it is not
being used) using the bridge power-down switch. Figure 22
shows how the bridge power-down switch is used. The switch
can withstand 30 mA of continuous current, and it has an on
resistance of 10 Ω maximum.
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