參數(shù)資料
型號(hào): DSD1794DBR
廠商: Texas Instruments, Inc.
英文描述: 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER
中文描述: 24位192 kHz的采樣,高級(jí)分段,音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐
文件頁數(shù): 42/47頁
文件大?。?/td> 417K
代理商: DSD1794DBR
SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
42
DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode
DSD = 1 (Register 20, B5)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
Register 17
R/W
0
0
1
0
0
0
0
R/W
0
0
1
0
0
0
1
Register 18
Register 19
R/W
0
0
1
0
0
1
0
DMF1
DMF0
R/W
0
0
1
0
0
1
1
REV
OPE
Register 20
Register 21
Register 22
NOTE: indicates that function is disabled. No operation even if data bit is set
R/W
0
0
1
0
1
0
0
SRST
1
MONO
CHSL
OS1
OS0
R
0
0
1
0
1
0
1
DZ1
DZ0
R
0
0
1
0
1
1
0
ZFGR
ZFGL
DMF[1:0]: Analog FIR Performance Selection
Default value: 00
DMF[1:0]
00
01
10
11
Analog-FIR Performance Select
FIR-1 (default)
FIR-2
FIR-3
FIR-4
Plots for the four analog FIR filter responses are shown in the
TYPICAL PERFORMANCE CURVES
section of this
data sheet.
OS[1:0]: Analog-FIR Operation-Speed Selection
Default value: 00
OS[1:0]
00
01
10
11
Operation Speed Select
f
DBCK
(default)
f
DBCK
/2
Reserved
f
DBCK
/4
The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before
setting the DSD bit to 1.
Requirements for System Clock
The bit clock (DBCK) for the DSD mode is required at pin 3 of the DSD1794. The frequency of the bit clock can be
N times the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL and DSDR is required to meet the same setup-and hold-time
specifications as shown in Figure 42.
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