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參數(shù)資料
| 型號： | DSD1794DBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER |
| 中文描述： | 24位192 kHz的采樣，高級分段，音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐 |
| 文件頁數(shù)： | 19/47頁 |
| 文件大?。?/td> | 417K |
| 代理商： | DSD1794DBR |
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SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
19
External Digital Filter Interface and Timing
The DSD1794 supports an external digital filter interface with a 3- or 4-wire synchronous serial port, which allows
the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific
Microsonics PMD200, or a programmable digital signal processor.
In the external DF mode, PLRCK (pin 4), PBCK (pin 6) and PDATA (pin 5) are defined as WDCK, the word clock;
BCK, the bit clock; and DATA, the monaural data, respectively. The external digital filter interface is selected by using
the DFTH bit of control register 20, which functions to bypass the internal digital filter of the DSD1794.
When the DFMS bit of control register 19 is set, the DSD1794 can process stereo data. In this case, DSDL (pin 1)
and DSDR (pin 2) are defined as L-channel data and R-channel data input, respectively.
Detailed information for the external digital filter interface mode is provided in the
APPLICATION FOR EXTERNAL
DIGITAL FILTER INTERFACE
section of this data sheet.
Direct Stream Digital (DSD) Format Interface and Timing
The DSD1794 supports the DSD-format interface operation, which includes out-of-band noise filtering using an
internal analog FIR filter. The DSD-format interface consists of a 3-wire synchronous serial port, which includes
DBCK (pin 3), DSDL (pin 1), and DSDR (pin 2). DBCK is the serial bit clock. DSDL and DSDR are the L-channel and
R-channel DSD data inputs, respectively. They are clocked into the DSD1794 on the rising edge of DBCK. PLRCK
(pin 4) and PBCK (pin 6) are connected to GND in the DSD mode. The DSD-format interface is activated by setting
the DSD bit of control register 20.
Detailed information for the DSD mode is provided in the
APPLICATION FOR DSD FORMAT (DSD MODE)
INTERFACE
section of this data sheet.
SERIAL CONTROL INTERFACE (I
2
C)
The DSD1794 supports the I
2
C serial bus and the data transmission protocol for standard and fast mode as a slave
device. This protocol is explained in I
2
C specification 2.0.
Slave Address
MSB
LSB
1
0
0
1
1
ADR1
ADR0
R/W
The DSD1794 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset
to 10011. The next two bits of the address byte are the device select bits which can be user-defined by the ADR1
and ADR0 terminals. A maximum of four DSD1794s can be connected on the same bus at one time. Each DSD1794
responds when it receives its own slave address.
Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data
if write or acknowledge if read, and stop condition. The DSD1794 supports only slave receivers and slave
transmitters.
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| DSD1796DBG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24B St Adv Segment Audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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