參數(shù)資料
型號： DSD1794DBR
廠商： Texas Instruments, Inc.
英文描述： 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER
中文描述： 24位192 kHz的采樣，高級分段，音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐
文件頁數(shù)： 29/47頁
文件大小： 417K
代理商： DSD1794DBR
SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
29
OS[1:0]: Delta-Sigma Oversampling Rate Selection
These bits are available for read and write.
Default value: 00
OS[1:0]
00
01
10
11
Operation Speed Select
64 times f
S
(default)
32 times f
S
128 times f
S
Reserved
The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the
designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example,
programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation
allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128 f
S
oversampling rate is not
available at sampling rates above 100 kHz. If the 128 f
S
oversampling rate is selected, a system clock of more than
256 f
S
is required.
In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter.
B15
R/W
B14
0
B13
0
B12
1
B11
0
B10
1
B9
0
B8
1
B7
RSV
B6
RSV
B5
RSV
B4
RSV
B3
RSV
B2
DZ1
B1
DZ0
B0
Register 21
PCMZ
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
DZ[1:0]: DSD Zero Output Enable
These bits are available for read and write.
Default value: 00
DZ[1:0]
00
01
1x
Zero Output Enable
Disabled (default)
Even pattern detect
96
H
pattern detect
The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode. The
DSD1794 sets zero flags when the number of 1s and 0s are equal in every 8 bits of DSD input data, or the DSD input
data is 1001 0110 continuously for 200 ms.
PCMZ: PCM Zero Output Enable
These bits are available for read and write.
Default value: 1
PCMZ = 0
PCMZ = 1
PCM zero output disabled
PCM zero output enabled (default)
The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode. The
DSD1794 sets the zero flags when the input data is continuously zero for 1024 LRCKs in the PCM mode or 1024
×
8 WCKs in the external filter mode.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 22
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV
ZFGR
ZFGL
相關(guān)PDF資料
PDF描述
DSD2410
DSD2425
DSD2450
DLD2410
DLD2425
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSD1794DBRG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DSD1796 制造商:TI 制造商全稱:Texas Instruments 功能描述:24BIT 192KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
DSD1796DB 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit Ster Adv Seg Delta-Sig Audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1796DBG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24B St Adv Segment Audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1796DBR 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit Ster Adv Seg Delta-Sig Audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*