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參數(shù)資料
| 型號： | DSD1794DBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER |
| 中文描述： | 24位192 kHz的采樣，高級分段，音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐 |
| 文件頁數(shù)： | 17/47頁 |
| 文件大?。?/td> | 417K |
| 代理商： | DSD1794DBR |
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SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
17
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes PLRCK (pin 4), PBCK (pin 6), and PDATA (pin 5). PBCK
is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of
the audio interface. Serial data is clocked into the DSD1794 on the rising edge of PBCK. PLRCK is the serial audio
left/right word clock.
The DSD1794 requires the synchronization of PLRCK and the system clock, but does not need a specific phase
relation between PLRCK and the system clock.
If the relationship between PLRCK and the system clock changes more than
±
6 PBCK, internal operation is initialized
within 1/f
S
and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the
system clock is completed.
PCM Audio Data Formats and Timing
The DSD1794 supports industry-standard audio data formats, including standard right-justified, I
2
S, and left-justified.
The data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0], in control
register 18. The default data format is 24-bit I
2
S. All formats require binary twos-complement, MSB-first audio data.
Figure 27 shows a detailed timing diagram for the serial audio interface.
PDATA
t(BCH)
50% of VDD
PBCK
PLRCK
t(BCL)
t(LB)
t(BCY)
t(DS)
t(DH)
50% of VDD
50% of VDD
t(BL)
PARAMETERS
MIN
MAX
UNITS
t(BCY)
t(BCL)
t(BCH)
t(BL)
t(LB)
t(DS)
t(DH)
—
PBCK pulse cycle time
70
ns
PBCK pulse duration, LOW
30
ns
PBCK pulse duration, HIGH
30
ns
PBCK rising edge to PLRCK edge
10
ns
PLRCK edge to PBCK rising edge
10
ns
PDATA Setup time
10
ns
PDATA hold time
10
50%
±
2 bit clocks
ns
PLRCK clock data
Figure 27. Timing of Audio Interface
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