參數(shù)資料
型號： DSD1794DBR
廠商： Texas Instruments, Inc.
英文描述： 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER
中文描述： 24位192 kHz的采樣，高級分段，音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐
文件頁數(shù)： 25/47頁
文件大?。?/td> 417K
代理商： DSD1794DBR
SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
25
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 18
R/W
0
0
1
0
0
1
0
ATLD
FMT2
FMT1
FMT0
DMF1
DMF0
DME
MUTE
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATLD: Attenuation Load Control
This bit is available for read and write.
Default value: 0
ATLD = 0
ATLD = 1
Attenuation control disabled (default)
Attenuation control enabled
The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD = 0,
the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16
and 17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.
FMT[2:0]: Audio Interface Data Format
These bits are available for read and write.
Default value: 101
For the external digital filter interface mode (DFTH mode), this register is operated as shown in the
Application for
Interfacing With an External Digital Filter
section of this data sheet.
FMT[2:0]
000
001
010
011
100
101
110
111
Audio Data Format Selection
16-bit standard format, right-justified data
20-bit standard format, right-justified data
24-bit standard format, right-justified data
24-bit MSB-first, left-justified format data
16-bit I
2
S-format data
24-bit I
2
S-format data (default)
Reserved
Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
These bits are available for read and write.
Default value: 00
DMF[1:0]
00
01
10
11
De-Emphasis Sampling Frequency Selection
Disabled (default)
48 kHz
44.1 kHz
32 kHz
The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is
enabled by setting the DME bit. The de-emphasis curves are shown in the
TYPICAL PERFORMANCE CURVES
section of this data sheet.
For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter
response plots are shown in the
APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
section of
this data sheet.
相關(guān)PDF資料
PDF描述
DSD2410
DSD2425
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DLD2410
DLD2425
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