參數(shù)資料
型號： DSD1794DBR
廠商： Texas Instruments, Inc.
英文描述： 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER
中文描述： 24位192 kHz的采樣，高級分段，音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐
文件頁數(shù)： 37/47頁
文件大?。?/td> 417K
代理商： DSD1794DBR
SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
37
DATA
t(BCH)
50% of VDD
BCK
WDCK
t(BCL)
t(LB)
t(BCY)
t(DS)
t(DH)
50% of VDD
50% of VDD
t(BL)
PARAMETER
MIN
MAX
UNITS
t(BCY)
t(BCL)
t(BCH)
t(BL)
t(LB)
t(DS)
t(DH)
BCK pulse cycle time
20
ns
BCK pulse duration, LOW
7
ns
BCK pulse duration, HIGH
7
ns
BCK rising edge to WDCK falling edge
5
ns
WDCK falling edge to BCK rising edge
5
ns
DATA setup time
5
ns
DATA hold time
5
ns
Figure 39. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
Functions Available in the External Digital Filter Mode
The external digital filter mode allows access to the majority of the DSD1794 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions which are modified when using this mode selection.
B15
R/W
B14
0
B13
0
B12
1
B11
0
B10
0
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
Register 17
Register 18
R/W
0
0
1
0
0
0
1
R/W
0
0
1
0
0
1
0
FMT2
FMT1
FMT0
Register 19
Register 20
R/W
0
0
1
0
0
1
1
REV
OPE
DFMS
INZD
R/W
0
0
1
0
1
0
0
SRST
0
1
MONO
CHSL
OS1
OS0
Register 21
Register 22
NOTE: 1 indicates that the bit is required for selection of external digital filter mode.
indicates that function is disabled. No operation even if data bit is set
R/W
0
0
1
0
1
0
1
PCMZ
R
0
0
1
0
1
1
0
ZFGR
ZFGL
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
000
001
010
Other
Audio Data Format Select
16-bit right-justified format (default)
20-bit right-justified format
24-bit right-justified format
N/A
相關(guān)PDF資料
PDF描述
DSD2410
DSD2425
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DLD2410
DLD2425
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