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參數(shù)資料
| 型號： | DSD1794DBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER |
| 中文描述： | 24位192 kHz的采樣，高級分段，音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐 |
| 文件頁數(shù)： | 38/47頁 |
| 文件大?。?/td> | 417K |
| 代理商： | DSD1794DBR |
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SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
38
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection
Default value: 00
OS[1:0]
00
01
10
11
Operation Speed Select
8 times WDCK (default)
4 times WDCK
16 times WDCK
Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter and
the delta-sigma modulator. For example, if the external digital filter is 8
×
oversampling, and the user selects
OS[1:0] = 00, then the delta-sigma modulator oversamples by 8
×
, resulting in an effective oversampling rate of 64
×
.
The 16
×
WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected
is 16
×
WDCK, the system clock frequency must be over 256 f
S
.
APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
Bit Clock
DSD Decoder
PDATA
5
6
7
PBCK
SCK
DSDL
1
2
3
4
DSDR
DBCK
PLRCK
DSD1794
DATA_L
DATA_R
System Clock (1)
(1)The system clock is necessary for the initilaization sequence and the I2C interface operation.
Figure 40. Connection Diagram in DSD Mode
Feature
This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CD (SACD) applications.
The DSD mode is accessed by programming the following bit in the corresponding control register.
DSD = 1 (register 20)
The DSD mode provides a low-pass filtering function to convert the 1-bit oversampled data stream to the analog
domain. The filtering is provided using an analog FIR filter structure. Four FIR responses are available, and are
selected by the DMF[1:0] bits of control register 18.
The DSD bit must be set before inputting DSD data, otherwise the DSD1794 erroneously detects the TDMCA mode,
and commands are not accepted through the serial control interface.
Pin Assignment When DSD Format Interface
DSDL (pin 1): L-channel DSD data input
DSDR (pin 2): R-channel DSD data input
DBCK (pin 3): Bit clock (BCK) for DSD data
Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
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| DSD1796DBR | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit Ster Adv Seg Delta-Sig Audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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