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| 型號(hào)： | DSD1794DBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER |
| 中文描述： | 24位192 kHz的采樣，高級(jí)分段，音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐 |
| 文件頁(yè)數(shù)： | 24/47頁(yè) |
| 文件大?。?/td> | 417K |
| 代理商： | DSD1794DBR |
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SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
24
Register Map
The mode control register map is shown in Table 3. Registers 16–21 include an R/W bit, which determines whether
a register read (R/W = 1) or write (R/W = 0) operation is performed. Register 22 is read-only.
Table 3. Mode Control Register Map
B15
R/W
B14
0
B13
0
B12
1
B11
0
B10
0
B9
0
B8
0
B7
ATL7
B6
ATL6
B5
ATL5
B4
ATL4
B3
ATL3
B2
ATL2
B1
ATL1
B0
ATL0
Register 16
Register 17
R/W
0
0
1
0
0
0
1
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Register 18
R/W
0
0
1
0
0
1
0
ATLD
FMT2
FMT1
FMT0
DMF1
DMF0
DME
MUTE
Register 19
R/W
0
0
1
0
0
1
1
REV
ATS1
ATS0
OPE
ZOE
DFMS
FLT
INZD
Register 20
R/W
0
0
1
0
1
0
0
RSV
SRST
DSD
DFTH
MONO
CHSL
OS1
OS0
Register 21
R/W
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
DZ1
DZ0
PCMZ
Register 22
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV
ZFGR
ZFGL
Register Definitions
B15
R/W
B14
0
B13
0
B12
1
B11
0
B10
0
B9
0
B8
0
B7
ATL7
B6
ATL6
B5
ATL5
B4
ATL4
B3
ATL3
B2
ATL2
B1
ATL1
B0
ATL0
Register 16
Register 17
R/W
0
0
1
0
0
0
1
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATx[7:0]: Digital Attenuation Level Setting
These bits are available for read and write.
Default value: 1111 1111b
Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB
steps. Alternatively, the attenuator can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control
register 18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The
attenuation level can be set using the following formula:
Attenuation level (dB) = 0.5 dB
(ATx[7:0]
DEC
– 255)
where ATx[7:0]
DEC
= 0 through 255
For ATx[7:0]
DEC
= 0 through 14, the attenuator is set to infinite attenuation. Table 4 shows attenuation levels for
various settings.
Table 4. Digital Attenuation Levels
ATx[7:0]
1111 1111b
1111 1110b
1111 1101b
Decimal Value
255
254
253
Attenuation Level Setting
0 dB, no attenuation (default)
–0.5 dB
–1.0 dB
0001 0000b
0000 1111b
0000 1110b
16
15
14
–119.5 dB
–120.0 dB
Mute
0000 0000b
0
Mute
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