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參數(shù)資料
| 型號： | DSD1794DBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER |
| 中文描述： | 24位192 kHz的采樣，高級分段，音頻STRRO數(shù)字至ALALOG轉(zhuǎn)爐 |
| 文件頁數(shù)： | 26/47頁 |
| 文件大?。?/td> | 417K |
| 代理商： | DSD1794DBR |
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SLES077A MARCH 2003 REVISED NOVEMBER 2003
www.ti.com
26
DME: Digital De-Emphasis Control
This bit is available for read and write.
Default value: 0
DME = 0
DME = 1
De-emphasis disabled (default)
De-emphasis enabled
The DME bit is used to enable or disable the de-emphasis function for both channels.
MUTE: Soft Mute Control
This bit is available for read and write.
Default value: 0
MUTE = 0
MUTE = 1
MUTE disabled (default)
MUTE enabled
The MUTE bit is used to enable or disable the soft mute function for both channels.
Soft mute is operated as a 256-step attenuator. The speed for each step to –
∞
dB (mute) is determined by the
attenuation rate selected in the ATS register.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 19
R/W
0
0
1
0
0
1
1
REV
ATS1
ATS0
OPE
ZOE
DFMS
FLT
INZD
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
REV: Output Phase Reversal
This bit is available for read and write.
Default value: 0
REV = 0
REV = 1
Normal output (default)
Inverted output
The REV bit is used to invert the output phase for both channels.
ATS[1:0]: Attenuation Rate Select
These bits are available for read and write.
Default value: 00
ATS[1:0]
00
01
10
11
Attenuation Rate Selection
Every PLRCK (default)
PLRCK/2
PLRCK/4
PLRCK/8
The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level
transitions.
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