參數(shù)資料
型號: DS33Z11+
廠商: Maxim Integrated Products
文件頁數(shù): 92/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 169-CSBGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 7
應用: 數(shù)據(jù)傳輸
接口: SPI/并聯(lián)
電源電壓: 1.8V, 3.3V
封裝/外殼: 169-LBGA,CSPBGA
供應商設備封裝: 169-CSBGA(14x14)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS33Z11 Ethernet Mapper
26 of 172
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
BGA(100)
TYPE
FUNCTION
JTAG INTERFACE
JTRST
E6
Ipu
Active-Low JTAG Reset:
JTRST is used to
asynchronously reset the test access port controller. After
power-up, a rising edge on
JTRST will reset the test port
and cause the device IO enter the JTAG DEVICE ID
mode. Pulling
JTRST low restores normal device
operation.
JTRST is pulled HIGH internally via a 10k
resistor operation. If boundary scan is not used, this pin
should be held low.
JTCLK
D4
Ipu
JTAG Clock: This signal is used to shift data into JTDI on
the rising edge and out of JTDO on the falling edge.
JTDO
E5
Oz
JTAG Data Out: Test instructions and data are clocked
out of this pin on the falling edge of JTCLK. If not used,
this pin should be left unconnected.
JTDI
E4
Ipu
JTAG Data In: Test instructions and data are clocked into
this pin on the rising edge of JTCLK. This pin has a 10k
pullup resistor.
JTMS
F7
Ipu
JTAG Mode Select: This pin is sampled on the rising
edge of JTCLK and is used to place the test access port
into the various defined IEEE 1149.1 states. This pin has
a 10k
pullup resistor.
POWER SUPPLIES
VDD3.3
G5–G10,
H5–H10
A7, D4–
D8, H10
I
Connect to 3.3V Power Supply
VDD1.8
D2, D3,
D12, E3,
E11, E12,
F4, F10,
J4, K4,
L3, L12,
M13
A1, F6,
F10, H2,
J10
I
Connect to 1.8V Power Supply
VSS
A12, D1,
E7, E8,
F8, F9,
F12, F13,
J5–J11,
K3, K5,
K7, K8,
K9, K10,
K12
A5, B4,
E4–E7
I
Connect to the Common Supply Ground
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