參數(shù)資料
型號: DS33Z11+
廠商: Maxim Integrated Products
文件頁數(shù): 114/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 169-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 7
應(yīng)用: 數(shù)據(jù)傳輸
接口: SPI/并聯(lián)
電源電壓: 1.8V, 3.3V
封裝/外殼: 169-LBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 169-CSBGA(14x14)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS33Z11 Ethernet Mapper
46 of 172
Figure 8-6 DS33Z11 Configured as a DCE in MII Mode
MAC
TXD[3:0]
RXD[3:0]
TX_CLK
RX_CLK
TX_ERR
RX_ERR
TX_EN
RX_CRS
COL_DET
DTE
DCE
TX_EN
RXDV
MDC
MDIO
TXD[3:0]
RXD[3:0]
TX_CLK
DS33Z11
WAN
MAC
RX_CLK
RXDV
RX_CRS
MDIO
MDC
Rx
Tx
Rx
Arbiter
8.14 Ethernet MAC
Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the
SU.MACWD0-3 registers to be written with 4 bytes of data. The address must be written to SU.MACAWL and
SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one to
SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33Z11 when the operation is complete.
Reading from the MAC registers requires the SU.MACRADH and SU.MACRADL registers to be written with the
address for the read operation. A read command is issued by writing a one to SU.MACRWC.MCRW and a zero
to SU.MACRWC.MCS. SU.MACRWC.MCS is cleared by the DS33Z11 when the operation is complete. After
MCS is clear, valid data is available in SU.MACRD0-SU.MACRD3. Note that only one operation can be initiated
(read or write) at one time. Data cannot be written or read from the MAC registers until the MCS bit has been
cleared by the device. The MAC Registers are detailed in the following table.
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DS33Z41DK 功能描述:以太網(wǎng)開發(fā)工具 DS33Z41 Dev Kit RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: