參數(shù)資料
型號: DS33Z11+
廠商: Maxim Integrated Products
文件頁數(shù): 75/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 169-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 7
應(yīng)用: 數(shù)據(jù)傳輸
接口: SPI/并聯(lián)
電源電壓: 1.8V, 3.3V
封裝/外殼: 169-LBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 169-CSBGA(14x14)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS33Z11 Ethernet Mapper
166 of 172
Figure 12-2 TAP Controller State Diagram
12.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When
the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO.
While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial
output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the
controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift
register to the instruction parallel output. Instructions supported by the DS33Z11 and its respective operational
binary codes are shown in Table 12-1.
1
0
1
11
1
11
1
00
0
1
0
1
0
Select
DR-Scan
Capture DR
Shift DR
Exit DR
Pause DR
Exit2 DR
Update DR
Select
IR-Scan
Capture IR
Shift IR
Exit IR
Pause IR
Exit2 IR
Update IR
Test Logic
Reset
Run Test/
Idle
0
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