參數(shù)資料
型號: DS33Z11+
廠商: Maxim Integrated Products
文件頁數(shù): 106/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 169-CSBGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 7
應用: 數(shù)據(jù)傳輸
接口: SPI/并聯(lián)
電源電壓: 1.8V, 3.3V
封裝/外殼: 169-LBGA,CSPBGA
供應商設備封裝: 169-CSBGA(14x14)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS33Z11 Ethernet Mapper
39 of 172
It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers
must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data
may be transmitted. The proper procedure for setting up a connection follows:
Set up the queue sizes for both transmit and receive queue (AR.TQSC1 and AR.RQSC1).
Set up the high/low thresholds and interrupt enables if desired (GL.TRQIE, LI.TQTIE, SU.QRIE)
Reset all the pointers for the connection desired (GL.C1QPR)
Set up the connections (GL.CON1)
If a connection is disconnected, reset the queue pointers after the disconnection.
Table 8-3 Registers Related to Connections and Queues
Register
Enables connection between the Ethernet Interface and the Serial Interface.
Note that once connection is set up, then the queues and thresholds can be
setup for that connection.
Size for the Transmit Queue in Number of 32—2K packets.
Size for the Receive Queue in Number of 32—2K packets.
Interrupt enable for items related to the connections at the global level
Interrupt enable status for items related to the connections at the global level
Enables for the Transmit queue crossing high and low thresholds
Latched status bits for connection high and low thresholds for the transmit
queue.
Enables for the receive queue crossing high and low thresholds
Latched status bits for receive queue high and low thresholds.
Resets the connection pointer.
8.11 Arbiter
The Arbiter manages the transport between the Ethernet port and the Serial port. It is responsible for queuing and
dequeuing packets to a single external SDRAM. The arbiter handles requests from the HDLC and MAC to
transfer data to and from the SDRAM.
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