參數(shù)資料
型號: DS33Z11+
廠商: Maxim Integrated Products
文件頁數(shù): 157/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 169-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 7
應(yīng)用: 數(shù)據(jù)傳輸
接口: SPI/并聯(lián)
電源電壓: 1.8V, 3.3V
封裝/外殼: 169-LBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 169-CSBGA(14x14)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS33Z11 Ethernet Mapper
85 of 172
Register Name:
BPCLR
Register Description:
BERT Pattern Configuration Low Register
Register Address:
82h
Bit #
7
6
5
4
3
2
1
0
Name
-
QRSS
PTS
PLF4
PLF3
PLF2
PLF1
PLF0
Default
0
The BERT’s BPCLR, BPCHR, and BSPB registers are used for polynomial-based pattern generation, with a
formula of x
n + xy + 1. The initial value for x (the seed) is placed in the BSPB (bert seed/pattern) register. The
BERT generates a series of bits by iteration of the formula.
Bit 6: QRSS Enable (QRSS) When 0, the pattern generator configuration is controlled by PTS, PLF[0:4], and
PTF[0:4], and BSP[0:31]. When 1, the pattern generator configuration is forced to a QRSS pattern with a
generating polynomial of x
20 + x17 + 1. The output of the pattern generator is forced to one if the next fourteen
output bits are all zero.
Bit 5: Pattern Type Select (PTS) When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]) These five bits control the “l(fā)ength” feedback of the pattern
generator. The “l(fā)ength” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n. The values possible are
outlined in Section 8.15.
Register Name:
BPCHR
Register Description:
BERT Pattern Configuration High Register
Register Address:
83h
Bit #
7
6
5
4
3
2
1
0
Name
-
PTF4
PTF3
PTF2
PTF1
PTF0
Default
0
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]) These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y. The
values possible are outlined in Section 8.15.
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