參數(shù)資料
型號: DS33Z11+
廠商: Maxim Integrated Products
文件頁數(shù): 49/172頁
文件大小: 0K
描述: IC MAPPER ETHERNET 169-CSBGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 7
應用: 數(shù)據(jù)傳輸
接口: SPI/并聯(lián)
電源電壓: 1.8V, 3.3V
封裝/外殼: 169-LBGA,CSPBGA
供應商設備封裝: 169-CSBGA(14x14)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS33Z11 Ethernet Mapper
142 of 172
10 FUNCTIONAL TIMING
10.1 Functional Serial I/O Timing
The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces. TDEN is an
input signal that can be used to enable or block the TSER data. The “shaded bits” are not clocked by the
DS33Z11. The TDEN must occur one bit before the effected bit in the TSER stream. Note that polarity of the
TDEN is selectable through LI.TSLCR. In the figure below, TDEN is active low , allowing the bits to clock and
inactive high, causing the next data bit not be clocked. TCLK can be gapped as shown in the following figure.
Similarly, the receiver function is governed by RCLKI, RDEN and RSER. RSER data will not be provided to the
receiver for the bits blocked when RDEN is inactive. The RDEN polarity can be programmed by LI.RSLCR. The
RDEN signal must be coincident with the RSER bit that needs to be blocked.
Figure 10-1 TX Serial Interface Functional Timing
TCLK
gapped
TSER
TCLKI
TDEN
TSER
TCLK Gapped
TSER
Figure 10-2 RX Serial Interface Functional Timing
TSER
RCLKI
RDEN
RSER
RCLK Gapped
RSER
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