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參數資料
| 型號： | CLRC632 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Multiple Protocol Contactless Reader IC |
| 中文描述： | 多協(xié)議非接觸式讀卡器IC |
| 文件頁數： | 84/163頁 |
| 文件大?。?/td> | 948K |
| 代理商： | CLRC632 |
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Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
84
Confidential
8.2
Implementation of Interrupt Request Handling
8.2.1
CONTROLLING INTERRUPTS AND THEIR STATUS
The CL RC632 informs the μ-Processor about the interrupt request source by setting the according bit in the
InterruptRq Register
. The relevance of each interrupt request bit as source for an interrupt may be masked
with the interrupt enable bits of the
InterruptEn Register
.
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
InterruptEn
SetIEn
rfu
TimerIEn
TxIEn
RxIEn
IdleIEn
HiAlertIEn
LoAlertIEn
InterruptRq
SetIRq
rfu
TimerIRq
TxIRq
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
Table 8-2: Interrupt Control Registers
If any interrupt request flag is set to 1 (showing that an interrupt request is pending) and the corresponding
interrupt enable flag is set the status flag
IRq
in the
PrimaryStatus Register
is set to 1. Furthermore different
interrupt sources can be set active simultaneously. Therefore, all interrupt request bits are ‘OR’ed and
connected to the flag
IRq
and forwarded to pin IRQ.
8.2.2
ACCESSING THE INTERRUPT REGISTERS
The interrupt request bits are set automatically by the internal state machines of the CL RC632. Additionally
the μ-Processor has access in order to set or to clear them.
A special implementation of the
InterruptRq
and the
InterruptEn
Register allows the change a single bit
status without influencing the other ones. If a specific interrupt register shall be set to one, the bit
SetIxx
has
to be set to 1 and simultaneously the specific bit has to be set to 1 too. Vice versa, if a specific interrupt flag
shall be cleared, a zero has to be written to the
SetIxx
and simultaneously the specific address of the
interrupt register has to be set to 1. If a bit content shall not be changed during the setting or clearing phase
a zero has to be written to the specific bit location.
Example: writing 3F
hex
to the
InterruptRq Register
clears all bits as
SetIRq
in this case is set to 0 and all
other bits are set to 1. Writing 81
hex
sets bit
LoAlertIRq
to 1 and leaves all other bits untouched.
8.3
Configuration of Pin IRQ
The logic level of the status flag
IRq
is visible at pin IRQ. In addition, the signal on pin IRQ may be controlled
by the following bits of the
IRQPinConfig Register
:
IRQInv
: if set to 0, the signal on pin IRQ is equal to the logic level of bit
IRq
.
If set to 1, the signal on pin IRQ is inverted with respect to bit
IRq
.
IRQPushPull
: if set to 1, pin IRQ has standard CMOS output characteristics
otherwise it is an open drain output and an external resistor is necessary to achieve a HIGH level at this
pin.
Note: During the Reset Phase (see 11.2)
IRQInv
is set to 1 and
IRQPushPull
to 0. This results in a high
impedance at pin IRQ.
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相關代理商/技術參數 |
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|---|---|
| CLRC63201T/0FE | 制造商:NXP Semiconductors 功能描述: |
| CLRC63201T/0FE,112 | 功能描述:RFID應答器 I.CODE HS READER RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| CLRC63201T/0FE,118 | 制造商:NXP Semiconductors 功能描述:Interface Misc |
| CLRC63201T/0FE112 | 制造商:NXP Semiconductors 功能描述:CNTCLESS RC 5V ISO14443 + ISO15693 |
| CLRC663 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC |
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