參數(shù)資料
型號(hào)： CLRC632
廠商： NXP Semiconductors N.V.
英文描述： Multiple Protocol Contactless Reader IC
中文描述： 多協(xié)議非接觸式讀卡器IC
文件頁(yè)數(shù)： 119/163頁(yè)
文件大?。?/td> 948K
代理商： CLRC632
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Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
119
Confidential
18.4.2 RECEIVE COMMAND 16
HEX
Command
Code
hex
Action
Arguments and Data
Returned Data
Receive
16
Activates Receiver Circuitry
-
Data Stream
The
Receive-Command
activates the receiver circuitry. All data received from the RF interface is returned via
the FIFO buffer. The
Receive-Command
can be started either by the μ-Processor or automatically during
execution of the
Transceive-Command
.
Note: This command may be used for test purposes only, since there is no timing relation to the
Transmit-
Command
.
18.4.2.1 Working with the Receive Command
After starting the
Receive Command
the internal state machine decrements the value set in the
RxWait-
Register
with every bit-clock. From 3 down to 1 the analog receiver circuitry is prepared and activated. When
the counter reaches 0, the receiver starts monitoring the incoming signal at the RF-interface. If the signal
strength reaches a level higher than the value set in the
MinLevel-Register
it finally starts decoding. The
decoder stops, if no more signal can be detected on the receiver input pin Rx. The decoder indicates
termination of operation by setting bit
RxIRq
.
The different phases of the receive sequence may be monitored by watching
ModemState
of the
PrimaryStatus-Register
(see 18.4.4).
Note: Since the counter values from 3 to 0 are necessary to initialise the analog receiver circuitry the
minimum value for
RxWait
is 3.
18.4.2.2 RF-Channel Redundancy and Framing
The decoder expects a SOF pattern at the beginning of each data stream. If a SOF is detected, it activates
the serial to parallel converter and gathers the incoming data bits. Every completed byte is forwarded to the
FIFO. If an EOF pattern is detected or the signal strength falls below
MinLevel
set in the
RxThreshold
Register
, the receiver and the decoder stop, the
Idle-Command
is entered and an appropriate response for
the μ-Processor is generated (interrupt request activated, status flags set).
If bit
RxCRCEn
in the
ChannelRedundancy Register
is set a CRC block is expected. The CRC block may be
one byte or two bytes according to bit
CRC8
in the
ChannelRedundancy Register
.
Remark: The received CRC block is not forwarded to the FIFO buffer if it is correct. This is realised by
shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the
defined CRC). The CRC block remains in this internal buffer. As a consequence all data bytes are available
in the FIFO buffer one or two bytes delayed.
If the CRC fails all received bytes are forwarded to the FIFO buffer (including the faulty CRC itself).
If
ParityEn
is set in the
ChannelRedundancy Register
a parity bit is expected after each byte. If bit
ParityOdd
is set to 1, the expected parity is an odd parity, otherwise an even parity is expected.
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