參數(shù)資料
型號： CLRC632
廠商： NXP Semiconductors N.V.
英文描述： Multiple Protocol Contactless Reader IC
中文描述： 多協(xié)議非接觸式讀卡器IC
文件頁數(shù)： 11/163頁
文件大小： 948K
代理商： CLRC632
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
11
Confidential
3.2
Pin Description
Pin Types: I...Input;
O...Output;
PWR...Power
PIN
SYMBOL
TYPE
DESCRIPTION
1
OSCIN
I
Crystal Oscillator Input
: input to the inverting amplifier of the oscillator.
This pin is also the input for an externally generated clock (f
osc
= 13.56 MHz).
Interrupt Request
: output to signal an interrupt event
MIFARE
Interface Input
: accepts a digital, serial data stream according to
ISO14443A (MIFARE
)
MIFARE
Interface Output
: delivers a serial data stream according to ISO14443A
(MIFARE
)
I
CODE
Interface Output
: delivers a serial data stream according to I
CODE1 and
ISO 15693
2
IRQ
O
3
MFIN
I
4
2
MFOUT
O
5
TX1
O
Transmitter 1
: delivers the modulated 13.56 MHz energy carrier
6
TVDD
PWR
Transmitter Power Supply
: supplies the output stage of TX1 and TX2
7
TX2
O
Transmitter 2
: delivers the modulated 13.56 MHz energy carrier
8
TVSS
PWR
Transmitter Ground
: supplies the output stage of TX1 and TX2
9
NCS
I
Not Chip Select
: selects and activates the μ-Processor interface of the CL RC632
NWR
I
Not Write
: strobe to write data (applied on D0 to D7) into the CL RC632 register
R/NW
I
Read Not Write
: selects if a read or write cycle shall be performed.
10
1
nWrite
I
Not Write
: selects if a read or write cycle shall be performed
NRD
I
Not Read
: strobe to read data from the CL RC632 register (applied on D0 to D7)
NDS
I
Not Data Strobe
: strobe for the read and the write cycle
11
1
nDStrb
I
Not Data Strobe
: strobe for the read and the write cycle
12
DVSS
PWR
Digital Ground
13
D0
O
Master In Slave Out (MISO),
SPI interface,
D0 to D7
I/O
8 Bit Bi-directional Data Bus
13
…
20
1
AD0 to AD7
I/O
8 Bit Bi-directional Address and Data Bus
ALE
I
Address Latch Enable
:
signal to latch AD0 to AD5 into the internal address latch
when HIGH.
AS
I
Address Strobe
: strobe signal to latch AD0 to AD5 into the internal address latch
when HIGH.
nAStrb
I
Not Address Strobe
: strobe signal to latch AD0 to AD5 into the internal address latch
when LOW.
21
1
NSS
I
Not Slave Select:
strobe for the SPI communication
A0
I
Address Line 0
: Bit 0 of register address
nWait
O
Not Wait:
signals with LOW that an access-cycle may started and with HIGH that it
may be finished.
22
1
MOSI
I
Master Out Slave In,
SPI interface
PIN Description (continued)
1
These pins offer different functionality according to the selected μ-Processor interface type. For detailed
information, refer to chapter 4.
2
The SL RC400 uses the name SIGOUT for the MFOUT pin. The CLRC 632 functionality includes the test possibilities
for the SL RC 400 using the pin MFOUT
.
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