參數(shù)資料
型號: CLRC632
廠商: NXP Semiconductors N.V.
英文描述: Multiple Protocol Contactless Reader IC
中文描述: 多協(xié)議非接觸式讀卡器IC
文件頁數(shù): 72/163頁
文件大小: 948K
代理商: CLRC632
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
72
Confidential
5.4
Modes of Register Addressing
Three mechanisms are valid to operate with the CL RC632:
Initiating functions and controlling data manipulation by executing
commands
Configuring electrical and functional behaviour via a set of
configuration bits
Monitoring the state of the CL RC632 by reading
status flags
The commands, configuration bits and flags are accessed via the μ-Processor interface.
The CL RC632 can internally address 64 registers. This basically requires six address lines.
5.4.1
PAGING MECHANISM
The CL RC632 register set is segmented into 8 pages with 8 register each. The
Page-Register
can always
be addressed, no matter which page is currently selected.
5.4.2
DEDICATED ADDRESS BUS
Using the CL RC632 with dedicated address bus, the μ-Processor defines three address lines via the
address pins A0, A1, and A2. This allows addressing within a page. To switch between registers in different
pages the paging mechanism needs then to be used.
The following table shows how the register address is assembled:
Register Bit:
UsePageSelect
Register-Address
1
PageSelect2
PageSelect1 PageSelect0
A2
A1
A0
Table 5-3: Dedicated Address Bus: Assembling the Register Address
5.4.3
MULTIPLEXED ADDRESS BUS
Using the CL RC632 with multiplexed address bus, the μ-Processor may define all 6 address lines at once.
In this case either the paging mechanism or linear addressing may be used.
The following table shows how the register address is assembled:
Interface Bus Type
Register Bit:
UsePageSelect
Register-Address
Multiplexed Address Bus
(paging mode)
1
PageSelect2
PageSelect1 PageSelect0
AD2
AD1
AD0
Multiplexed Address Bus
(linear addressing)
0
AD5
AD4
AD3
AD2
AD1
AD0
Table 5-4: Multiplexed Address Bus: Assembling the Register Address
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