參數(shù)資料
型號(hào): CLRC632
廠商: NXP Semiconductors N.V.
英文描述: Multiple Protocol Contactless Reader IC
中文描述: 多協(xié)議非接觸式讀卡器IC
文件頁數(shù): 80/163頁
文件大小: 948K
代理商: CLRC632
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
80
Confidential
7
FIFO BUFFER
7.1
Overview
An 8x64 bit FIFO buffer is implemented in the CL RC632 acting as a parallel-to-parallel converter. It buffers
the input and output data stream between the μ-Processor and the internals of the CL RC632. Thus, it is
possible to handle data streams with lengths of up to 64 bytes without taking timing constraints into account.
7.2
Accessing the FIFO Buffer
7.2.1
ACCESS RULES
The FIFO-buffer input and output data bus is connected to the
FIFOData Register
. Writing to this register
stores one byte in the FIFO-buffer and increments the internal FIFO-buffer write-pointer. Reading from this
register shows the FIFO-buffer contents stored at the FIFO-buffer read-pointer and increments the FIFO-
buffer read-pointer. The distance between the write- and read-pointer can be obtained by reading the
FIFOLength Register
.
When the μ-Processor starts a command, the CL RC632 may, while the command is in progress, access the
FIFO-buffer according to that command. Physically only one FIFO-buffer is implemented, which can be used
in input- and output direction. Therefore the μ-Processor has to take care, not to access the FIFO-buffer in
an unintended way.
The following table gives an overview on FIFO access during command processing:
μ-Processor is allowed to
Active Command
Write to FIFO
Read from FIFO
Remark
StartUp
-
-
Idle
-
-
Transmit
9
-
Receive
-
9
Transceive
9
9
μ-Processor has to know the actual state of the command
(transmitting or receiving)
WriteE2
9
-
ReadE2
9
9
The μ-Processor has to prepare the arguments,
afterwards only reading is allowed
LoadKeyE2
9
-
LoadKey
9
-
Authent1
9
-
Authent2
-
-
LoadConfig
9
-
CalcCRC
9
-
Table 7-1: Allowed Access to the FIFO-Buffer
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