參數(shù)資料
型號: CLRC632
廠商: NXP Semiconductors N.V.
英文描述: Multiple Protocol Contactless Reader IC
中文描述: 多協(xié)議非接觸式讀卡器IC
文件頁數(shù): 154/163頁
文件大?。?/td> 948K
代理商: CLRC632
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
154
Confidential
22.5.2.2 Bus Timing for Common Read/Write Strobe
SYMBOL
t
LHLL
t
AVLL
t
LLAX
t
LLSL
t
CLSL
t
SHCH
t
SLDV,R
t
SHDZ
t
SLDV,W
t
SHDX
t
SHRX
t
SLSH
t
AVSL
t
SHAX
t
SHSL
t
RVSL
PARAMETER
AS pulse width
MIN
20
15
8
15
0
0
8
8
65
30
8
150
8
MAX
65
20
35
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Multiplexed Address Bus valid to AS low (Address Set Up Time)
Multiplexed Address Bus valid after AS low (Address Hold Time)
AS low to NDS low
NCS low to NDS low
NDS high to NCS high
NDS low to DATA valid (for read cycle)
NDS low to DATA high impedance (read cycle)
NDS low to DATA valid (for write cycle)
DATA hold after NDS high (write cycle, Hold Time)
R/NW hold after NDS high
NDS pulse width
Separated Address Bus valid to NDS low (Hold Time)
Separated Address Bus valid after NDS high (Set Up Time)
period between sequenced read/write accesses
R/NW valid to NDS low
Table 22-11: Timing Specification for Common Read/Write Strobe
Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t
care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.
t
AVLL
ALE
t
LHLL
NCS
t
CLSL
t
SHDX
t
SHDZ
D0 ... D7
D0 ... D7
t
SLDV,R
t
SLDV,W
t
LLAX
t
SHSL
NDS
t
SLSH
t
LLSL
t
SHSL
A0 ... A2
t
AVSL
Multiplexed Addressbus
A0 ... A2
t
SHAX
Separated Addressbus
A0 ... A2
t
RVSL
R/NW
t
SHCH
t
SHRX
Figure 22-2: Timing Diagram for Common Read/Write Strobe
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