參數(shù)資料
型號: CLRC632
廠商: NXP Semiconductors N.V.
英文描述: Multiple Protocol Contactless Reader IC
中文描述: 多協(xié)議非接觸式讀卡器IC
文件頁數(shù): 83/163頁
文件大?。?/td> 948K
代理商: CLRC632
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
83
Confidential
8
INTERRUPT REQUEST SYSTEM
8.1
Overview
The CL RC632 indicates certain events by setting bit
IRq
in the
PrimaryStatus-Register
and, in addition, by
activating pin IRQ. The signal on pin IRQ may be used to interrupt the μ-Processor using its interrupt
handling capabilities. This allows the implementation of efficient μ-Processor software.
8.1.1
INTERRUPT SOURCES OVERVIEW
The following table shows the integrated interrupt flags, the related source and the condition for its setting.
The interrupt flag
TimerIRq
indicates an interrupt set by the timer unit. The setting is done when the timer
decrements from 1 either down to zero (
TAutoRestart flag disabled
) or to the TPreLoad value if TAutoRestart
is enabled.
The
TxIRq
bit indicates interrupts from different sources. If the transmitter is active and the state changes
from sending data to transmitting the end of frame pattern, the transmitter unit sets automatically the interrupt
bit. The CRC coprocessor sets
TxIRq
after having processed all data from the FIFO buffer. This is indicated
by the flag
CRCReady
= 1. If the E
2
Prom programming has finished the
TxIRq
bit is set, indicated by the bit
E2Ready
= 1.
The
RxIRq
flag indicates an interrupt when the end of the received data is detected.
The flag
IdleIRq
is set if a command finishes and the content of the command register changes to idle.
The flag
HiAlertIRq
is set to 1 if the
HiAlert
bit is set to one, that means the FIFO buffer has reached the level
indicated by the bit
WaterLevel
, see chapter 7.4.
The flag
LoAlertIRq
is set to 1 if the
LoAlert
bit is set to one, that means the FIFO buffer has reached the
level indicated by the bit
WaterLevel
, see chapter 7.4.
Interrupt Flag
Interrupt Source
Is set automatically, when
TimerIRq
Timer Unit
the timer counts from 1 to 0
Transmitter
a data stream, transmitted to the card, ends
CRC-Coprocessor
all data from the FIFO buffer has been processed
TxIRq
E2PROM
all data from the FIFO buffer has been programmed
RxIRq
Receiver
a data stream, received from the card, ends
IdleIRq
Command Register
a command execution finishes
HiAlertIRq
FIFO-buffer
the FIFO-buffer is getting full
LoAlertIRq
FIFO-buffer
the FIFO-buffer is getting empty
Table 8-1: Interrupt Sources
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